公开(公告)号：US20150357248A1

公开(公告)日：2015-12-10

申请号：US14828281

申请日：2015-08-17

申请人： Tessera Advanced Technologies, Inc.

发明人： Nozomu MATSUZAKI ,  Hiroyuki MIZUNO ,  Masashi HORIGUCHI

IPC分类号： H01L21/8238 ,  H01L29/423

CPC分类号： H01L21/823857 ,  B82Y99/00 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/0883 ,  H01L29/42364 ,  Y10S438/981 ,  Y10S977/936

摘要： The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.

摘要翻译： 半导体集成电路器件在相同的硅衬底上采用具有在源极和栅极之间或其漏极和栅极之间流动的不同大小的隧道电流的多种MOS晶体管。 这些MOS晶体管包括隧道电流增加的MOS晶体管，其中至少一个用于构成器件的主电路。 多种MOS晶体管还包括隧道电流减少或耗尽的MOS晶体管，其中至少一个用于控制电路。 该控制电路插入在主电路和两个电源单元中的至少一个之间。

公开(公告)号：US09034709B2

公开(公告)日：2015-05-19

申请号：US14380967

申请日：2013-02-20

申请人： Asahi Kasei Microdevices Corporation

发明人： Shogo Katsuki ,  Toshiro Sakamoto

IPC分类号： H01L27/112 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/02 ,  H01L21/324 ,  H01L29/78

CPC分类号： H01L21/823462 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/26506 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/2822 ,  H01L21/324 ,  H01L29/51 ,  H01L29/78 ,  Y10S438/981

摘要： A method for manufacturing a semiconductor device, includes forming a first gate oxide film in each of a first region and a second region by thermally oxidizing a silicon substrate, forming a CVD oxide film on the first gate oxide film, implanting fluorine into each of the first region and the second region through the CVD oxide film and the first gate oxide film, removing the CVD oxide film from the first gate oxide film in the second region, removing the first gate oxide film from the second region, and forming a second gate oxide film in the second region by thermally oxidizing the silicon substrate.

摘要翻译： 一种半导体器件的制造方法，包括通过热氧化硅衬底，在第一栅极氧化膜上形成CVD氧化膜，在第一区域和第二区域的每一个中形成第一栅氧化膜，将氟注入到 通过CVD氧化膜和第一栅氧化膜形成第一区域和第二区域，从第二区域中的第一栅极氧化膜去除CVD氧化膜，从第二区域去除第一栅极氧化膜，形成第二栅极 通过热氧化硅衬底而在第二区域中形成氧化膜。

公开(公告)号：US08084328B2

公开(公告)日：2011-12-27

申请号：US12923889

申请日：2010-10-13

申请人： Zhen-Cheng Wu ,  Yung-Cheng Lu ,  Pi-Tsung Chen ,  Ying-Tsung Chen

发明人： Zhen-Cheng Wu ,  Yung-Cheng Lu ,  Pi-Tsung Chen ,  Ying-Tsung Chen

IPC分类号： H01I21/8234

CPC分类号： H01L21/823462 ,  H01L27/088 ,  Y10S438/981

摘要： A semiconductor device includes a semiconductor substrate, wherein the semiconductor substrate includes a core area for core circuits and a peripheral area for peripheral circuits. The semiconductor device includes a core oxide on the semiconductor substrate in the core area, a portion of the core oxide being nitrided, a first polysilicon pattern on the core oxide, an I/O oxide including pure oxide on the semiconductor substrate in the peripheral area, and a second polysilicon pattern on the I/O oxide.

摘要翻译： 半导体器件包括半导体衬底，其中半导体衬底包括用于核心电路的芯区域和用于外围电路的外围区域。 半导体器件在核心区域中的半导体衬底上具有核心氧化物，核心氧化物的一部分被氮化，核心氧化物上的第一多晶硅图案，在周边区域中的半导体衬底上的纯氧化物的I / O氧化物 ，以及I / O氧化物上的第二多晶硅图案。

公开(公告)号：US07973391B2

公开(公告)日：2011-07-05

申请号：US12128620

申请日：2008-05-29

申请人： Joseph C. Fjelstad ,  Kevin P. Grundy ,  Para K. Segaram ,  Gary Yasumura

发明人： Joseph C. Fjelstad ,  Kevin P. Grundy ,  Para K. Segaram ,  Gary Yasumura

IPC分类号： H01L23/58

CPC分类号： H05K1/0243 ,  G01R31/2822 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6627 ,  H01L2223/6633 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/1903 ,  H01L2924/19039 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01P3/08 ,  H01P5/028 ,  H05K1/024 ,  H05K2201/0191 ,  H05K2201/09154 ,  H05K2201/09727 ,  Y10S438/981 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Disclosed are tapered dielectric and conductor structures which provide controlled impedance interconnection while signal conductor lines transition from finer pitches to coarser pitches thereby obviating electrical discontinuities generally associated with changes of circuit contact pitch. Also disclosed are methods for the construction of the devices and applications therefore.

摘要翻译： 公开了锥形电介质和导体结构，其提供受控的阻抗互连，同时信号导体线从更细的间距转换到较粗的间距，从而消除通常与电路接触间距的变化相关的电中断。 还公开了用于构造装置和应用的方法。

公开(公告)号：US07851834B2

公开(公告)日：2010-12-14

申请号：US12715941

申请日：2010-03-02

申请人： Hongning Yang ,  Geoffrey W. Perkins ,  Jiang-Kai Zuo

发明人： Hongning Yang ,  Geoffrey W. Perkins ,  Jiang-Kai Zuo

IPC分类号： H01L29/94

CPC分类号： H01L29/7833 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/6659 ,  Y10S438/981

摘要： Embodiments of a cascode amplifier (CA) include a bottom transistor with a relatively thin gate dielectric and higher ratio of channel length to width and a series coupled top transistor with a relatively thick gate dielectric and a lower ratio of channel length to width. A cascode current mirror (CCM) is formed using a coupled pair of CAs, one forming the reference current (RC) side and the other forming the mirror current side of the CCM. The gates of the bottom transistors are tied together and to the common node between the series coupled bottom and top transistors of the RC side, and the gates of the top transistors are coupled together and to the top drain node of the RC side. The area of the CCM can be substantially shrunk without adverse affect on the matching, noise performance and maximum allowable operating voltage.

摘要翻译： 共源共栅放大器（CA）的实施例包括具有相对薄的栅极介质和沟道长度与宽度的较高比的底部晶体管和具有相对较厚的栅极电介质和沟道长度与宽度的较小比的串联耦合顶部晶体管。 使用耦合的一对CA形成共源共栅电流镜（CCM），一对形成基准电流（RC）侧，另一个形成CCM的反射镜电流侧。 底部晶体管的栅极连接在RC侧的串联耦合的底部和顶部晶体管之间的公共节点，并且顶部晶体管的栅极耦合在一起并连接到RC侧的顶部漏极节点。 CCM的面积可以大幅收缩，对匹配，噪声性能和最大允许工作电压没有不利影响。

公开(公告)号：US07799649B2

公开(公告)日：2010-09-21

申请号：US11279602

申请日：2006-04-13

申请人： Hiroaki Niimi ,  Reima Tapani Laaksonen

发明人： Hiroaki Niimi ,  Reima Tapani Laaksonen

IPC分类号： H01L21/336

CPC分类号： H01L21/823462 ,  Y10S438/981

摘要： The present invention provides a method for manufacturing a semiconductor device. The method, in one embodiment, includes forming a silicon oxide masking layer over a substrate in a first active region and a second active region of a semiconductor device, patterning the silicon oxide masking layer to expose the substrate in the first active region. The method further includes forming a layer of dielectric material over the substrate in the first active region, the patterned silicon oxide masking layer protecting the substrate from the layer of dielectric material in the second active region.

摘要翻译： 本发明提供一种制造半导体器件的方法。 在一个实施例中，该方法包括在半导体器件的第一有源区和第二有源区中的衬底上形成氧化硅屏蔽层，图案化氧化硅屏蔽层以暴露第一有源区中的衬底。 该方法还包括在第一有源区中的衬底上形成介电材料层，图案化氧化硅屏蔽层保护衬底免受第二有源区中的介电材料层的影响。

公开(公告)号：US20090321798A1

公开(公告)日：2009-12-31

申请号：US12553408

申请日：2009-09-03

申请人： Dae Hong MIN

发明人： Dae Hong MIN

IPC分类号： H01L31/112

CPC分类号： H01L27/14632 ,  H01L27/14687 ,  Y10S438/981

摘要： Disclosed are a CMOS sensor and a method of fabricating the CMOS sensor. The method includes the steps of: forming a first USG layer on an entire surface of a semiconductor substrate including a cell area and a scribe area; masking the cell area, and then removing the first USG layer formed on the scribe area; forming a SiN layer on the entire surface of the semiconductor substrate; masking the cell area, and then removing the SiN layer formed on the scribe area; forming a second USG layer on the entire surface of the semiconductor substrate; and masking the scribe area, and then removing the second USG layer formed on the cell area. The USG layer is only formed on the scribe layer without the SiN layer, so that SiN particles do not drop onto the USG layer during the sintering process.

摘要翻译： 公开了CMOS传感器和制造CMOS传感器的方法。 该方法包括以下步骤：在包括单元区域和划线区域的半导体衬底的整个表面上形成第一USG层; 掩蔽单元区域，然后移除在划线区域上形成的第一USG层; 在半导体衬底的整个表面上形成SiN层; 掩蔽细胞区域，然后除去形成在划线区域上的SiN层; 在所述半导体衬底的整个表面上形成第二USG层; 并掩蔽划线区域，然后去除在单元区域上形成的第二USG层。 USG层仅形成在没有SiN层的划线层上，使得SiN颗粒在烧结过程中不会落到USG层上。

公开(公告)号：US07585736B2

公开(公告)日：2009-09-08

申请号：US11723092

申请日：2007-03-16

申请人： Yoichi Fukushima

发明人： Yoichi Fukushima

IPC分类号： H01L21/336

CPC分类号： H01L21/823462 ,  H01L29/78 ,  Y10S438/981

摘要： A method of manufacturing a semiconductor device includes steps (a) to (d). The step (a) is a step of forming a first insulating film and a nitride film on a semiconductor substrate in this order. The step (b) is a step of removing said first insulating film and said nitride film in a first region while leaving said first insulating film and said nitride film in a second region. The step (c) is a step of forming a second insulating film on said semiconductor substrate in said first region. Here, a thickness of said second insulating film is different from that of said first insulating film. A third insulating film is formed on said nitride film in said second region along with the formation of said second insulating film. The step (d) is a step of removing said third insulating film and said nitride film in said second region.

摘要翻译： 制造半导体器件的方法包括步骤（a）至（d）。 步骤（a）是在半导体衬底上依次形成第一绝缘膜和氮化物膜的步骤。 步骤（b）是在第一区域中除去所述第一绝缘膜和所述氮化物膜，同时将第一绝缘膜和所述氮化物膜留在第二区域中的步骤。 步骤（c）是在所述第一区域中在所述半导体衬底上形成第二绝缘膜的步骤。 这里，所述第二绝缘膜的厚度与所述第一绝缘膜的厚度不同。 在形成所述第二绝缘膜的同时，在所述第二区域中的所述氮化物膜上形成第三绝缘膜。 步骤（d）是在所述第二区域中去除所述第三绝缘膜和所述氮化物膜的步骤。

公开(公告)号：US07550349B2

公开(公告)日：2009-06-23

申请号：US11637705

申请日：2006-12-13

申请人： Chul Jin Yoon

发明人： Chul Jin Yoon

IPC分类号： H01L21/336

CPC分类号： H01L21/28238 ,  H01L21/022 ,  H01L21/0223 ,  H01L21/3144 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/11568 ,  H01L27/11573 ,  Y10S438/981

摘要： A method for forming gate dielectric layers having different thicknesses is provided, The method includes forming a lower oxide layer, a nitride layer, and an upper oxide layer on a semiconductor substrate; performing a first deglaze process to the semiconductor substrate keeping the lower oxide layer, the nitride layer, and the upper oxide layer in a first region, while removing the nitride layer and the upper oxide layer in second, third, and fourth regions; forming the first gate dielectric layer having a first thickness in the second, third, and fourth regions; performing a second deglaze process to the first gate dielectric layer in the third region, thereby forming a second gate dielectric layer having a second thickness; and performing a third deglaze process on the first gate dielectric layer on the fourth region, thereby forming a third gate dielectric layer having a third thickness.

摘要翻译： 提供一种形成具有不同厚度的栅介质层的方法。该方法包括在半导体衬底上形成低氧化层，氮化物层和上氧化物层; 在第二区域中去除氮化物层和上部氧化物层的同时，在第一区域内对保持低氧化物层，氮化物层和上部氧化物层的半导体衬底进行第一脱灰处理; 在所述第二，第三和第四区域中形成具有第一厚度的所述第一栅极介电层; 对所述第三区域中的所述第一栅极电介质层进行第二脱灰处理，从而形成具有第二厚度的第二栅极介电层; 以及对所述第四区域上的所述第一栅极电介质层进行第三脱灰处理，由此形成具有第三厚度的第三栅极电介质层。

公开(公告)号：US07541661B2

公开(公告)日：2009-06-02

申请号：US11614469

申请日：2006-12-21

申请人： Hideki Yasuoka ,  Masami Kouketsu ,  Susumu Ishida ,  Kazunari Saitou

发明人： Hideki Yasuoka ,  Masami Kouketsu ,  Susumu Ishida ,  Kazunari Saitou

IPC分类号： H01L27/092

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823892 ,  H01L27/0629 ,  H01L27/092 ,  Y10S438/981

摘要： Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the second region. The present invention makes it possible to raise the threshold voltage of a parasitic MOS and in addition, to suppress occurrence of an NBT phenomenon.

摘要翻译： 提供一种半导体集成电路器件的制造方法，该半导体集成电路器件在第一区域具有多个第一MISFET以及第二区域中的多个第二MISFET，其包括在第一MISFET形成区域的两个相邻区域之间形成第一绝缘膜， 在第二区域中的第一区域和第二MISFET形成区域; 在所述第一和第二区域中的每个中的所述第一绝缘膜之间的半导体衬底的表面上形成第二绝缘膜; 在所述第二绝缘膜上沉积第三绝缘膜; 在所述第二区域中在所述第三绝缘膜上形成第一导电膜; 在从所述第一区域去除所述第三绝缘膜和所述第二绝缘膜之后，在所述第一区域中的所述半导体衬底的表面上形成第四绝缘膜; 以及在所述第四绝缘膜上形成第二导电膜; 其中所述第三绝缘膜保留在所述第二区域中的所述第一绝缘膜上。 本发明使得可以提高寄生MOS的阈值电压，并且还抑制NBT现象的发生。