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    Process for manufacturing a non-volatile memory cell with a floating gate region autoaligned to the isolation and with a high coupling coefficient
    1.
    发明申请
    Process for manufacturing a non-volatile memory cell with a floating gate region autoaligned to the isolation and with a high coupling coefficient 有权
    用于制造具有自动对准到隔离并具有高耦合系数的浮动栅极区域的非易失性存储单元的工艺

    公开(公告)号：US20020025631A1

    公开(公告)日：2002-02-28

    申请号：US09900501

    申请日：2001-07-06

    Applicant: STMicroelectronics S.r.l.

    Inventor： Roberto Bez ,  Emilio Camerlenghi ,  Stefano Ratti

    IPC: H01L021/336

    CPC classification number: H01L27/11521 ,  H01L27/115

    Abstract: A process for fabricating non-volatile memory cells on a semiconductor substrate includes forming a stack structure comprised of a first polysilicon layer isolated from the substrate by an oxide layer. The first polysilicon layer, oxide layer, and semiconductor substrate are cascade etched to define a first portion of a floating gate region of the cell and at least one trench bordering an active area of the memory cell. The at least one trench is filled with an isolation layer. The process further includes depositing a second polysilicon layer onto the whole exposed surface of the semiconductor, and etching the second polysilicon layer to expose the floating gate region formed in the first polysilicon layer, thereby forming extensions adjacent the above portion of the first polysilicon layer.

    Abstract translation: 用于在半导体衬底上制造非易失性存储单元的工艺包括由氧化物层形成由与衬底隔离的第一多晶硅层组成的堆叠结构。 级联蚀刻第一多晶硅层，氧化物层和半导体衬底以限定电池的浮动栅极区域的第一部分和与存储器单元的有效区域接合的至少一个沟槽。 至少一个沟槽填充有隔离层。 该方法还包括在半导体的整个暴露表面上沉积第二多晶硅层，以及蚀刻第二多晶硅层以暴露形成在第一多晶硅层中的浮栅区域，从而形成与第一多晶硅层的上述部分相邻的延伸。

    Manufacturing process for non-volatile floating gate memory cells integrated on a semiconductor substrate and comprised in a cell matrix with an associated control circuitry
    2.
    发明申请
    Manufacturing process for non-volatile floating gate memory cells integrated on a semiconductor substrate and comprised in a cell matrix with an associated control circuitry 有权
    集成在半导体衬底上并且包括在具有相关联的控制电路的单元矩阵中的非易失性浮动栅极存储器单元的制造工艺

    公开(公告)号：US20010016390A1

    公开(公告)日：2001-08-23

    申请号：US09730518

    申请日：2000-12-05

    Applicant: STMicroelectronics S.r.l.

    Inventor： Emilio Camerlenghi

    IPC: H01L021/336

    CPC classification number: H01L27/105 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11534

    Abstract: A process for forming floating gate non-volatile memory cells in a cell matrix with associated control circuitry comprising both N-channel and P-channel MOS transistors is provided. The process includes forming active areas in a substrate for the cell matrix and the associated control circuitry. A first thin oxide layer and a first polysilicon layer are deposited on the active areas to produce floating gate regions of the memory cells, and a second dielectric layer is deposited on the active areas. A second polysilicon layer is then deposited on the active areas. A masking and etching step is performed for exposing the substrate for the associated control circuitry followed by the deposition of a third polysilicon layer. The third polysilicon layer is defined to produce the gate regions of the transistors for the associated control circuitry while the third polysilicon layer is removed from the cell matrix. A self-aligned etching step is performed to define the gate regions of the memory cells, and dopants are implanted in the junction areas to produce the source/drain regions of the memory cells.

    Abstract translation: 提供了一种用于在具有包括N沟道和P沟道MOS晶体管的相关控制电路的单元矩阵中形成浮栅非易失性存储单元的过程。 该过程包括在用于单元矩阵和相关联的控制电路的衬底中形成有源区。 第一薄氧化物层和第一多晶硅层沉积在有源区上以产生存储器单元的浮动栅区，并且第二介电层沉积在有源区上。 然后将第二多晶硅层沉积在有源区上。 执行掩模和蚀刻步骤，用于暴露相关控制电路的衬底，随后沉积第三多晶硅层。 第三多晶硅层被定义为产生用于相关联的控制电路的晶体管的栅极区域，而第三多晶硅层从单元矩阵中移除。 执行自对准蚀刻步骤以限定存储器单元的栅极区域，并且在结区域中注入掺杂剂以产生存储器单元的源极/漏极区域。

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