公开(公告)号：US20240339489A1

公开(公告)日：2024-10-10

申请号：US18745970

申请日：2024-06-17

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Joo Woan CHO ,  Dae Ho SONG ,  Tae Hee LEE ,  Hyung Il JEON ,  Byeong Hwa CHOI

IPC: H01L27/15 ,  H01L23/00 ,  H01L23/48 ,  H01L25/18 ,  H01L27/105

CPC classification number: H01L27/156 ,  H01L23/481 ,  H01L24/06 ,  H01L25/18 ,  H01L24/05 ,  H01L24/08 ,  H01L24/16 ,  H01L24/48 ,  H01L27/105 ,  H01L2224/05025 ,  H01L2224/05541 ,  H01L2224/0613 ,  H01L2224/06181 ,  H01L2224/08225 ,  H01L2224/16145 ,  H01L2224/48229

Abstract: A display device includes a first substrate including a display area, a non-display area, and a plurality of pixel circuit units in the display area and the non-display area, a plurality of light emitting elements on the first substrate in the display area, the plurality of light emitting elements being electrically connected to the pixel circuit units, a hole mask layer on the first substrate and including a plurality of holes corresponding to the light emitting elements, a second substrate on the hole mask layer and including a plurality of open holes corresponding to the plurality of holes, and a plurality of light exit patterns in the plurality of the open holes of the second substrate corresponding to the plurality of holes, wherein each of the light exit patterns includes a first part in one of the plurality of open holes.

公开(公告)号：US12096699B2

公开(公告)日：2024-09-17

申请号：US18167325

申请日：2023-02-10

Applicant: TDK CORPORATION

Inventor： Tomoyuki Sasaki

IPC: G11C11/18 ,  G01R33/09 ,  G11B5/39 ,  G11C11/16 ,  H01F10/32 ,  H01L27/105 ,  H01L29/82 ,  H03B15/00 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85 ,  H10N52/00 ,  H10N52/01 ,  H10N52/80

CPC classification number: H10N52/00 ,  G01R33/098 ,  G11B5/39 ,  G11C11/161 ,  G11C11/1675 ,  G11C11/1697 ,  G11C11/18 ,  H01F10/32 ,  H01F10/3254 ,  H01F10/329 ,  H01L27/105 ,  H01L29/82 ,  H03B15/00 ,  H03B15/006 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85 ,  H10N52/01 ,  H10N52/80 ,  H01F10/3286

Abstract: This spin current magnetization rotational type magnetoresistive element includes a magnetoresistive effect element having a first ferromagnetic metal layer having a fixed magnetization orientation, a second ferromagnetic metal layer having a variable magnetization orientation, and a non-magnetic layer sandwiched between the first ferromagnetic metal layer and the second ferromagnetic metal layer, and spin-orbit torque wiring which extends in a direction that intersects the stacking direction of the magnetoresistive effect element, and is connected to the second ferromagnetic metal layer, wherein the electric current that flows through the magnetoresistive effect element and the electric current that flows through the spin-orbit torque wiring merge or are distributed in the portion where the magnetoresistive effect element and the spin-orbit torque wiring are connected.

公开(公告)号：US12068187B2

公开(公告)日：2024-08-20

申请号：US18424790

申请日：2024-01-27

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/683 ,  G11C8/16 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/00 ,  H01L23/367 ,  H01L25/00 ,  H01L25/065 ,  H10B20/20

CPC classification number: H01L21/6835 ,  G11C8/16 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  H10B10/00 ,  H10B10/125 ,  H10B12/053 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/3677 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/1214 ,  H01L27/1266 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H10B12/05 ,  H10B20/20

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layer; a second metal layer overlaying the first metal layer; and a second level including a second single crystal layer, the second level including second transistors and at least one third metal layer, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the second level includes a plurality of DRAM memory cells, where each of the plurality of DRAM memory cells includes at least one of the second transistors and one capacitor, where the second level is directly bonded to the first level, and where the bonded includes metal to metal bonds.

公开(公告)号：US20240266359A1

公开(公告)日：2024-08-08

申请号：US18640136

申请日：2024-04-19

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Atsushi UMEZAKI

IPC: H01L27/12 ,  G02F1/1333 ,  G02F1/1343 ,  G02F1/1345 ,  G02F1/1362 ,  G02F1/1368 ,  G09G3/3266 ,  G09G3/36 ,  G11C19/28 ,  H01H71/02 ,  H01H71/10 ,  H01L27/105 ,  H01L27/13 ,  H01L29/423 ,  H01L29/786 ,  H10K59/121 ,  H10K59/131

CPC classification number: H01L27/124 ,  G02F1/133345 ,  G02F1/136286 ,  G02F1/1368 ,  G09G3/3266 ,  G09G3/3677 ,  G11C19/28 ,  H01H71/02 ,  H01H71/10 ,  H01L27/105 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1222 ,  H01L27/1251 ,  H01L27/1255 ,  H01L29/78663 ,  H01L29/78678 ,  G02F1/134309 ,  G02F1/13454 ,  G02F1/13624 ,  G02F2202/103 ,  G09G3/3688 ,  G09G2300/0417 ,  G09G2300/0426 ,  G09G2320/043 ,  G09G2330/021 ,  G09G2330/023 ,  H01L27/13 ,  H01L29/42384 ,  H01L29/78696 ,  H10K59/1213 ,  H10K59/131

Abstract: By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes a problem for a transistor which constitutes a part of circuit that generates an AC pulse. A shift in threshold voltage of a transistor which easily deteriorates and a shift in threshold voltage of a turned-on transistor are suppressed by signal input to a gate electrode of the transistor which easily deteriorates through the turned-on transistor. In other words, a structure for applying an AC pulse to a gate electrode of a transistor which easily deteriorates through a transistor to a gate electrode of which a high potential (VDD) is applied, is included.

公开(公告)号：US20240224487A1

公开(公告)日：2024-07-04

申请号：US18604195

申请日：2024-03-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KI-IL KIM ,  Jung-gun YOU ,  Gi-gwan PARK

IPC: H10B10/00 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/105 ,  H01L29/78

CPC classification number: H10B10/12 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/105 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/7854

Abstract: A semiconductor device can include a field insulating film on a substrate and a fin-type pattern of a particular material, on the substrate, having a first sidewall and an opposing second sidewall. The fin-type pattern can include a first portion of the fin-type pattern that protrudes from an upper surface of the field insulating film and a second portion of the fin-type pattern disposed on the first portion. A third portion of the fin-type pattern can be disposed on the second portion where the third portion can be capped by a top rounded surface of the fin-type pattern and the first sidewall can have an undulated profile that spans the first, second and third portions.

公开(公告)号：US20240120339A1

公开(公告)日：2024-04-11

申请号：US18537929

申请日：2023-12-13

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI

IPC: H01L27/105 ,  G11C11/405 ,  G11C16/04 ,  H01L21/02 ,  H01L21/46 ,  H01L21/8258 ,  H01L27/12 ,  H01L29/06 ,  H01L29/786 ,  H10B41/10 ,  H10B41/20 ,  H10B41/30 ,  H10B41/35 ,  H10B41/70

CPC classification number: H01L27/105 ,  G11C11/405 ,  G11C16/0433 ,  H01L21/02664 ,  H01L21/46 ,  H01L21/8258 ,  H01L27/1225 ,  H01L29/06 ,  H01L29/7869 ,  H01L29/78693 ,  H10B41/10 ,  H10B41/20 ,  H10B41/30 ,  H10B41/35 ,  H10B41/70 ,  H01L27/0207

Abstract: Disclosed is a semiconductor device capable of functioning as a memory device. The memory device comprises a plurality of memory cells, and each of the memory cells contains a first transistor and a second transistor. The first transistor is provided over a substrate containing a semiconductor material and has a channel formation region in the substrate. The second transistor has an oxide semiconductor layer. The gate electrode of the first transistor and one of the source and drain electrodes of the second transistor are electrically connected to each other. The extremely low off current of the second transistor allows the data stored in the memory cell to be retained for a significantly long time even in the absence of supply of electric power.

公开(公告)号：US20240113014A1

公开(公告)日：2024-04-04

申请号：US18539193

申请日：2023-12-13

Applicant: Altera Corporation

Inventor： Krishna Bharath Kolluru ,  Atul Maheshwari ,  Mahesh Kumashikar ,  Md Altaf Hossain ,  Ankireddy Nalamalpu ,  Jeffrey Chromczak

IPC: H01L23/525 ,  H01L23/528 ,  H01L27/105

CPC classification number: H01L23/525 ,  H01L23/528 ,  H01L27/105

Abstract: An integrated circuit includes first external conductive pads, second external conductive pads, and third external conductive pads. The second external conductive pads are between the first external conductive pads and the third external conductive pads. Repair group circuitry is configurable to shift signal transmission away from one of the first external conductive pads to one of the third external conductive pads if the one of the first external conductive pads has a defect.

公开(公告)号：US20240029987A1

公开(公告)日：2024-01-25

申请号：US18480374

申请日：2023-10-03

Applicant: Kenneth G. Blemel ,  Kenneth D. Blemel ,  Benjamin Allen Bone ,  Jesse Min-Tze Adamczyk ,  Lara Rose Draelos ,  Mariana Flores-Olivas

Inventor： Kenneth G. Blemel ,  Kenneth D. Blemel ,  Benjamin Allen Bone ,  Jesse Min-Tze Adamczyk ,  Lara Rose Draelos ,  Mariana Flores-Olivas

IPC: H01H71/10 ,  H01H71/02 ,  H01H71/14 ,  H01H37/74 ,  G02F1/1333 ,  G02F1/1362 ,  G02F1/1368 ,  G09G3/3266 ,  G09G3/36 ,  G11C19/28 ,  H01L27/105 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01H71/10 ,  H01H71/02 ,  H01H71/14 ,  H01H37/74 ,  G02F1/133345 ,  G02F1/136286 ,  G02F1/1368 ,  G09G3/3266 ,  G09G3/3677 ,  G11C19/28 ,  H01L27/105 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1251 ,  H01L27/1255 ,  H01L29/78663 ,  H01L29/78678 ,  H01H2071/147 ,  G02F1/134309

Abstract: A method, apparatus, and system for protection from hazards of conductivity is disclosed using non-electrical means to disrupt electrical current with a thermovolumetric substance. The purpose of this invention is to prevent hazardous conditions from occurring by disrupting the flow of electrical current prior to the development of arc fault conditions.

公开(公告)号：US11876011B2

公开(公告)日：2024-01-16

申请号：US18215062

申请日：2023-06-27

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L29/792 ,  G11C8/16 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/367 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H10B20/20

CPC classification number: H01L21/6835 ,  G11C8/16 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  H10B10/00 ,  H10B10/125 ,  H10B12/053 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/3677 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/1214 ,  H01L27/1266 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/1579 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/30105 ,  H10B12/05 ,  H10B20/20

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where at least one of the second transistors includes a raised source or raised drain transistor structure, where the second level is directly bonded to the first level, and where the bonded includes direct oxide-to-oxide bonds.

公开(公告)号：US20230397447A1

公开(公告)日：2023-12-07

申请号：US18235995

申请日：2023-08-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

IPC: H10B99/00 ,  H01L27/12 ,  H01L29/24 ,  H01L29/16 ,  G11C11/405 ,  G11C16/04 ,  H01L27/105 ,  H01L27/118 ,  H10B41/20 ,  H10B41/70 ,  H10B69/00 ,  H01L29/786

CPC classification number: H10B99/00 ,  H01L27/1207 ,  H01L29/24 ,  H01L29/16 ,  G11C11/405 ,  G11C16/0433 ,  H01L27/105 ,  H01L27/11803 ,  H01L27/1225 ,  H10B41/20 ,  H10B41/70 ,  H10B69/00 ,  H01L29/7869 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/247 ,  H01L29/78693 ,  H01L29/78696 ,  G11C2211/4016 ,  H01L21/8221

Abstract: An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.