公开(公告)号：US11606083B2

公开(公告)日：2023-03-14

申请号：US17515069

申请日：2021-10-29

Applicant: STMicroelectronics S.r.l.

Inventor： Domenico Tripodi ,  Luca Giussani ,  Simone Ludwig Dalla Stella

IPC: H03K3/017 ,  H03K5/04 ,  H03K5/05 ,  H03L7/08

Abstract: A PWM signal generator circuit includes a multiphase clock generator that generates a number n of phase-shifted clock phases having the same clock period and being phase shifted by a time corresponding to a fraction 1/n of the clock period. The PWM signal generator circuit determines for each switch-on duration first and second integer numbers, and for each switch-off duration third and fourth integer numbers. The first integer number is indicative of the integer number of clock periods of the switch-on duration and the second integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-on duration. The third integer number is indicative of the integer number of clock periods of the switch-off duration, and the fourth integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-off duration.

公开(公告)号：US12015406B2

公开(公告)日：2024-06-18

申请号：US18175359

申请日：2023-02-27

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Domenico Tripodi ,  Luca Giussani ,  Simone Ludwig Dalla Stella

IPC: H03K3/017 ,  H03K5/04 ,  H03K5/05 ,  H03L7/08

CPC classification number: H03K3/017 ,  H03K5/04 ,  H03K5/05 ,  H03L7/08

Abstract: A PWM signal generator circuit includes a multiphase clock generator that generates a number n of phase-shifted clock phases having the same clock period and being phase shifted by a time corresponding to a fraction 1/n of the clock period. The PWM signal generator circuit determines for each switch-on duration first and second integer numbers, and for each switch-off duration third and fourth integer numbers. The first integer number is indicative of the integer number of clock periods of the switch-on duration and the second integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-on duration. The third integer number is indicative of the integer number of clock periods of the switch-off duration, and the fourth integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-off duration.

公开(公告)号：US11171632B2

公开(公告)日：2021-11-09

申请号：US17077833

申请日：2020-10-22

Applicant: STMicroelectronics S.r.l.

Inventor： Domenico Tripodi ,  Luca Giussani ,  Simone Ludwig Dalla Stella

IPC: H03K5/04 ,  H03K3/017 ,  H03K5/05 ,  H03L7/08

Abstract: A PWM signal generator circuit includes a multiphase clock generator that generates a number n of phase-shifted clock phases having the same clock period and being phase shifted by a time corresponding to a fraction 1/n of the clock period. The PWM signal generator circuit determines for each switch-on duration first and second integer numbers, and for each switch-off duration third and fourth integer numbers. The first integer number is indicative of the integer number of clock periods of the switch-on duration and the second integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-on duration. The third integer number is indicative of the integer number of clock periods of the switch-off duration, and the fourth integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-off duration.