公开(公告)号：US20190214910A1

公开(公告)日：2019-07-11

申请号：US16222557

申请日：2018-12-17

Applicant: STMicroelectronics Design and Application s.r.o. ,  STMicroelectronics S.r.l.

Inventor： Matthieu Thomas ,  Michele Suraci ,  Massimo Mazzucco

IPC: H02M3/158

CPC classification number: H02M3/1582 ,  H02M1/08 ,  H02M3/1584 ,  H02M3/1588 ,  H02M2001/0006 ,  H02M2001/0009

Abstract: A DC-DC converter circuit including at least: a first step down converter having a first pair of switching devices in a half bridge configuration. A second step down converter includes a second pair of switching devices in a half bridge configuration. The first and second step down converters are connected in parallel to an output node connected to an output coil and receive command signals. A feedback loop includes a synchronization module receiving the gate control signals of high side switching devices and adjusts as a function of the gate control signals a delay in a signal path from the command signal to each gate control signal of the high side switching device to synchronize the gate control signals.

公开(公告)号：US10720840B2

公开(公告)日：2020-07-21

申请号：US16222557

申请日：2018-12-17

Applicant: STMicroelectronics Design and Application s.r.o. ,  STMicroelectronics S.r.l.

Inventor： Matthieu Thomas ,  Michele Suraci ,  Massimo Mazzucco

IPC: H02M3/158 ,  H02M1/08 ,  H02M1/00

Abstract: A DC-DC converter circuit including at least: a first step down converter having a first pair of switching devices in a half bridge configuration. A second step down converter includes a second pair of switching devices in a half bridge configuration. The first and second step down converters are connected in parallel to an output node connected to an output coil and receive command signals. A feedback loop includes a synchronization module receiving the gate control signals of high side switching devices and adjusts as a function of the gate control signals a delay in a signal path from the command signal to each gate control signal of the high side switching device to synchronize the gate control signals.

公开(公告)号：US20220109369A1

公开(公告)日：2022-04-07

申请号：US17482961

申请日：2021-09-23

Applicant: STMicroelectronics S.r.l.

Inventor： Michele Suraci ,  Marco Borghese

IPC: H02M3/158 ,  H02M1/08 ,  H02M3/157 ,  H02M1/00

Abstract: In an embodiment a control circuit includes a low-power detection circuit configured to generate a control signal, wherein the low-power detection circuit is, when a driver circuit operates in a high-power mode, configured to determine a first temporal value indicative of a duration of a second phase (T2), detect whether a logic level of a zero current signal changes from a first logic level to a second logic level during the second phase (T2), in response to detecting that the logic level of the zero current signal changes from the first logic level to the second logic level, determine a second temporal value indicative of a time (TZC) elapsed between an instant (t3) when the logic level of the zero current signal changes from the first logic level to the second logic level during the second phase (T2) and the instant (t1) when the second phase (T2) ends, determine whether a ratio between the second temporal value (TZC) and the first temporal value (T2) is greater than a given number threshold value (TH), in response to determining that the ratio between the second temporal value (TZC) and the first temporal value (T2) is smaller than the given threshold value (TH), set a comparison signal to the first logic level indicating that the high-power mode is to be maintained, in response to determining that the ratio between the second temporal value (TZC) and the first temporal value (T2) is greater than the given threshold value (TH), set the comparison signal to the second logic level indicating that a low-power mode is to be activated and set the logic level of the control signal as a function of the comparison signal.

公开(公告)号：US11736009B2

公开(公告)日：2023-08-22

申请号：US17482961

申请日：2021-09-23

Applicant: STMicroelectronics S.r.l.

Inventor： Michele Suraci ,  Marco Borghese

IPC: H02M3/158 ,  H02M1/00

CPC classification number: H02M3/158 ,  H02M1/0032

Abstract: In an embodiment a control circuit includes a low-power detection circuit configured to generate a control signal, wherein the low-power detection circuit is, when a driver circuit operates in a high-power mode, configured to determine a first temporal value indicative of a duration of a second phase (T2), detect whether a logic level of a zero current signal changes from a first logic level to a second logic level during the second phase (T2), in response to detecting that the logic level of the zero current signal changes from the first logic level to the second logic level, determine a second temporal value indicative of a time (TZC) elapsed between an instant (t3) when the logic level of the zero current signal changes from the first logic level to the second logic level during the second phase (T2) and the instant (t1) when the second phase (T2) ends, determine whether a ratio between the second temporal value (TZC) and the first temporal value (T2) is greater than a given number threshold value (TH), in response to determining that the ratio between the second temporal value (TZC) and the first temporal value (T2) is smaller than the given threshold value (TH), set a comparison signal to the first logic level indicating that the high-power mode is to be maintained, in response to determining that the ratio between the second temporal value (TZC) and the first temporal value (T2) is greater than the given threshold value (TH), set the comparison signal to the second logic level indicating that a low-power mode is to be activated and set the logic level of the control signal as a function of the comparison signal.