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公开(公告)号：US11451127B2
公开(公告)日：2022-09-20
申请号：US16583901
申请日：2019-09-26
发明人： Marco Borghese , Simone Bellisai
摘要： A driver circuit includes an input node to receive an input signal for conversion at the output node of a converter, a driver node to provide to a switching power circuit stage in the converter a pulse-width modulated drive signal having an active time, first and second active time generation paths, and a selector circuit coupled to the first and second active time generation paths. The circuit is operable selectively in a first and a second operational mode wherein the driver node receives the pulse-width modulated drive signal having a first active time value generated in the first active time generation path, or a second active time value generated in the second active time generation path. The second active time generation path includes an active time generator network to provide a second active time value with the second active time value adaptively variable to match the first active time value.
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公开(公告)号：US12119746B2
公开(公告)日：2024-10-15
申请号：US17807466
申请日：2022-06-17
发明人： Marco Borghese , Mattia Carrera
CPC分类号： H02M3/158 , H02M1/0016 , H02M1/0022 , H02M1/0025
摘要： In an embodiment a circuit includes a voltage-controlled oscillator (VCO) circuit having a first node configured to receive a reference voltage, a second node configured to receive a feedback signal, which is a comparison signal, indicative of a variation of a regulated output voltage of an electronic voltage regulator with respect to the reference voltage and a third node configured to provide a clock signal having a clock period based on the reference voltage and the feedback signal, and a pulse-width modulated (PWM) signal generator circuit having a first node coupled to the VCO circuit and configured to receive the clock signal, a second node configured to receive an input signal proportional to an input voltage signal at an input node of the electronic voltage regulator and a third node configured to provide at least one PWM drive signal to one or more electronic switches of a switching stage based on the clock signal.
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公开(公告)号：US20220416656A1
公开(公告)日：2022-12-29
申请号：US17807466
申请日：2022-06-17
发明人： Marco Borghese , Mattia Carrera
摘要： In an embodiment a circuit includes a voltage-controlled oscillator (VCO) circuit having a first node configured to receive a reference voltage, a second node configured to receive a feedback signal, which is a comparison signal, indicative of a variation of a regulated output voltage of an electronic voltage regulator with respect to the reference voltage and a third node configured to provide a clock signal having a clock period based on the reference voltage and the feedback signal, and a pulse-width modulated (PWM) signal generator circuit having a first node coupled to the VCO circuit and configured to receive the clock signal, a second node configured to receive an input signal proportional to an input voltage signal at an input node of the electronic voltage regulator and a third node configured to provide at least one PWM drive signal to one or more electronic switches of a switching stage based on the clock signal.
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公开(公告)号：US20220385166A1
公开(公告)日：2022-12-01
申请号：US17887181
申请日：2022-08-12
发明人： Marco Borghese , Simone Bellisai
摘要： A driver circuit includes an input node to receive an input signal for conversion at the output node of a converter, a driver node to provide to a switching power circuit stage in the converter a pulse-width modulated drive signal having an active time, first and second active time generation paths, and a selector circuit coupled to the first and second active time generation paths. The circuit is operable selectively in a first and a second operational mode wherein the driver node receives the pulse-width modulated drive signal having a first active time value generated in the first active time generation path, or a second active time value generated in the second active time generation path. The second active time generation path includes an active time generator network to provide a second active time value with the second active time value adaptively variable to match the first active time value.
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公开(公告)号：US20220109369A1
公开(公告)日：2022-04-07
申请号：US17482961
申请日：2021-09-23
发明人： Michele Suraci , Marco Borghese
摘要： In an embodiment a control circuit includes a low-power detection circuit configured to generate a control signal, wherein the low-power detection circuit is, when a driver circuit operates in a high-power mode, configured to determine a first temporal value indicative of a duration of a second phase (T2), detect whether a logic level of a zero current signal changes from a first logic level to a second logic level during the second phase (T2), in response to detecting that the logic level of the zero current signal changes from the first logic level to the second logic level, determine a second temporal value indicative of a time (TZC) elapsed between an instant (t3) when the logic level of the zero current signal changes from the first logic level to the second logic level during the second phase (T2) and the instant (t1) when the second phase (T2) ends, determine whether a ratio between the second temporal value (TZC) and the first temporal value (T2) is greater than a given number threshold value (TH), in response to determining that the ratio between the second temporal value (TZC) and the first temporal value (T2) is smaller than the given threshold value (TH), set a comparison signal to the first logic level indicating that the high-power mode is to be maintained, in response to determining that the ratio between the second temporal value (TZC) and the first temporal value (T2) is greater than the given threshold value (TH), set the comparison signal to the second logic level indicating that a low-power mode is to be activated and set the logic level of the control signal as a function of the comparison signal.
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公开(公告)号：US12051965B2
公开(公告)日：2024-07-30
申请号：US17887181
申请日：2022-08-12
发明人： Marco Borghese , Simone Bellisai
CPC分类号： H02M1/08 , H02M1/0032 , H02M3/157 , H02M3/158
摘要： A driver circuit includes an input node to receive an input signal for conversion at the output node of a converter, a driver node to provide to a switching power circuit stage in the converter a pulse-width modulated drive signal having an active time, first and second active time generation paths, and a selector circuit coupled to the first and second active time generation paths. The circuit is operable selectively in a first and a second operational mode wherein the driver node receives the pulse-width modulated drive signal having a first active time value generated in the first active time generation path, or a second active time value generated in the second active time generation path. The second active time generation path includes an active time generator network to provide a second active time value with the second active time value adaptively variable to match the first active time value.
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公开(公告)号：US11736009B2
公开(公告)日：2023-08-22
申请号：US17482961
申请日：2021-09-23
发明人： Michele Suraci , Marco Borghese
CPC分类号： H02M3/158 , H02M1/0032
摘要： In an embodiment a control circuit includes a low-power detection circuit configured to generate a control signal, wherein the low-power detection circuit is, when a driver circuit operates in a high-power mode, configured to determine a first temporal value indicative of a duration of a second phase (T2), detect whether a logic level of a zero current signal changes from a first logic level to a second logic level during the second phase (T2), in response to detecting that the logic level of the zero current signal changes from the first logic level to the second logic level, determine a second temporal value indicative of a time (TZC) elapsed between an instant (t3) when the logic level of the zero current signal changes from the first logic level to the second logic level during the second phase (T2) and the instant (t1) when the second phase (T2) ends, determine whether a ratio between the second temporal value (TZC) and the first temporal value (T2) is greater than a given number threshold value (TH), in response to determining that the ratio between the second temporal value (TZC) and the first temporal value (T2) is smaller than the given threshold value (TH), set a comparison signal to the first logic level indicating that the high-power mode is to be maintained, in response to determining that the ratio between the second temporal value (TZC) and the first temporal value (T2) is greater than the given threshold value (TH), set the comparison signal to the second logic level indicating that a low-power mode is to be activated and set the logic level of the control signal as a function of the comparison signal.
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公开(公告)号：US11165346B2
公开(公告)日：2021-11-02
申请号：US16583845
申请日：2019-09-26
摘要： A converter circuit includes an input node for receiving an input signal and an output node for providing a converted output signal to a load, a switching power stage to receive the input signal and an on-off drive signal switching between an on-state and an off-state, and a reactive output network coupled to the switching power stage and configured to provide the converted output signal to the load. The converter circuit comprises a first feedback signal path configured to generate a PWM-modulated control signal for the switching power stage as a function of the converted output signal, and a second feedback signal path including an output variation sensing circuit to generate at least one output variation signal indicative of variations of the converted output signal over time.
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