公开(公告)号：US20020180054A1

公开(公告)日：2002-12-05

申请号：US10126936

申请日：2002-04-18

Applicant: STMicroelectronics S.r.l.

Inventor： Raffaele Zambrano ,  Cesare Artoni ,  Chiara Corvasce

IPC: H01L023/48

CPC classification number: H01L27/11502 ,  H01L21/76877

Abstract: An integrated device having: a first conductive region; a second conductive region; an insulating layer arranged between the first and the second conductive region; at least one through opening extending in the insulating layer between the first and the second conductive region; and a contact structure formed in the through opening and electrically connecting the first conductive region and the second conductive region. The contact structure is formed by a conductive material layer that coats the side surface and the bottom of the through opening and surrounds an empty region which is closed at the top by the second conductive region. The conductive material layer preferably comprises a titanium layer and a titanium-nitride layer arranged on top of one another.

Abstract translation: 一种集成装置，具有：第一导电区域; 第二导电区域; 布置在第一和第二导电区域之间的绝缘层; 至少一个通孔，其延伸在所述第一和第二导电区域之间的绝缘层中; 以及形成在所述通孔中并且电连接所述第一导电区域和所述第二导电区域的接触结构。 接触结构由覆盖通孔的侧表面和底部的导电材料层形成，并且包围由第二导电区域封闭在顶部的空区域。 导电材料层优选地包括彼此顶部布置的钛层和氮化钛层。

公开(公告)号：US20040029298A1

公开(公告)日：2004-02-12

申请号：US10635063

申请日：2003-08-05

Applicant: STMicroelectronics S.r.l.

Inventor： Giulio Casagrande ,  Raffaele Zambrano

IPC: H01L021/00

CPC classification number: H01L27/11502 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/11507

Abstract: Presented is a memory cell integrated in a semiconductor substrate that includes a MOS device connected in series to a capacitive element. The MOS device has first and second conduction terminals, and the capacitive element has a lower electrode covered with a layer of a dielectric material and capacitively coupled to an upper electrode. The MOS device is overlaid by at least one metallization layer that is covered with at least one top insulating layer. The capacitive element is formed on the top insulating layer. The cell is unique in that the metallization layer extends only between the MOS device and the capacitive element.

Abstract translation: 提出了集成在半导体衬底中的存储单元，其包括与电容元件串联连接的MOS器件。 MOS器件具有第一和第二导电端子，并且电容元件具有被电介质材料层覆盖并且电容耦合到上电极的下电极。 MOS器件由被至少一个顶部绝缘层覆盖的至少一个金属化层覆盖。 电容元件形成在顶部绝缘层上。 该电池是唯一的，因为金属化层仅在MOS器件和电容元件之间延伸。

公开(公告)号：US20020034106A1

公开(公告)日：2002-03-21

申请号：US09875448

申请日：2001-06-05

Applicant: STMicroelectronics S.r.l.

Inventor： Raffaele Zambrano

IPC: G11C007/00

CPC classification number: G11C17/12

Abstract: The ROM memory cell, not decodable by visual inspection comprises a substrate of semiconductor material having a first conductivity type, in particular Pnull. A first MOS device having a first threshold voltage is formed in a first portion of the substrate, and a MOS device having a second threshold voltage, greater than the first threshold voltage, is formed in a second portion of the substrate adjacent to the first portion. The second MOS device is a diode reverse biased during a reading phase of the ROM memory cell and comprises a source region having the first conductivity type and a drain region having a second conductivity type. The source region has a level of doping higher than that of the substrate.

公开(公告)号：US20040005725A1

公开(公告)日：2004-01-08

申请号：US10615961

申请日：2003-07-08

Applicant: STMicroelectronics S.r.l.

Inventor： Raffaele Zambrano

IPC: H01L021/00

CPC classification number: H01L27/11502 ,  H01L27/11507

Abstract: A contact structure for a ferroelectric memory device integrated in a semiconductor substrate and includes an appropriate control circuitry and a matrix array of ferroelectric memory cells, wherein each cell includes a MOS device connected to a ferroelectric capacitor. The MOS device has first and second conduction terminals and is covered with an insulating layer. The ferroelectric capacitor has a lower plate formed on the insulating layer above the first conduction terminals and connected electrically to the first conduction terminals, which lower plate is covered with a layer of a ferroelectric material and coupled capacitively to an upper plate. Advantageously, the contact structure comprises a plurality of plugs filled with a non-conductive material between the first conduction terminals and the ferroelectric capacitor, and comprises a plurality of plugs filled with a conductive material and coupled to the second conduction terminals or the control circuitry.

Abstract translation: 一种集成在半导体衬底中的铁电存储器件的接触结构，包括适当的控制电路和铁电存储器单元的矩阵阵列，其中每个单元包括连接到铁电电容器的MOS器件。 MOS器件具有第一和第二导电端子并被绝缘层覆盖。 铁电电容器具有形成在第一导电端子上方的绝缘层上的下板，并且电连接到第一导电端子，该下板被铁电材料层覆盖并电容耦合到上板。 有利地，接触结构包括在第一导电端子和铁电电容器之间填充有非导电材料的多个插塞，并且包括填充有导电材料并且耦合到第二导电端子或控制电路的多个插头。