公开(公告)号：US20040012009A1

公开(公告)日：2004-01-22

申请号：US10371154

申请日：2003-02-20

Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

Inventor： Giulio Casagrande ,  Roberto Bez ,  Fabio Pellizzer

IPC: H01L047/00 ,  H01L021/76

CPC classification number: G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

Abstract: An electronic semiconductor device has a sublithographic contact area between a first conductive region and a second conductive region. The first conductive region is cup-shaped and has vertical walls which extend, in top plan view, along a closed line of elongated shape. One of the walls of the first conductive region forms a first thin portion and has a first dimension in a first direction. The second conductive region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first and the second conductive regions are in direct electrical contact at their thin portions and form the sublithographic contact area. The elongated shape is chosen between rectangular and oval elongated in the first direction. Thereby, the dimensions of the contact area remain approximately constant even in presence of a small misalignment between the masks defining the conductive regions.

Abstract translation: 电子半导体器件具有在第一导电区域和第二导电区域之间的亚光刻接触面积。 第一导电区域是杯状的并且具有垂直壁，其在顶部平面图中沿着细长形状的封闭线延伸。 第一导电区域的一个壁形成第一薄部分并且具有在第一方向上的第一尺寸。 第二导电区域具有第二薄部分，该第二薄部分具有横向于第一尺寸的第二方向的第二亚光刻尺寸。 第一和第二导电区域在其薄部分处直接电接触并形成亚光刻接触区域。 细长形状选择在第一方向上伸长的矩形和椭圆形之间。 因此，即使在限定导电区域的掩模之间存在小的不对准的情况下，接触区域的尺寸也保持近似恒定。

公开(公告)号：US20040029298A1

公开(公告)日：2004-02-12

申请号：US10635063

申请日：2003-08-05

Applicant: STMicroelectronics S.r.l.

Inventor： Giulio Casagrande ,  Raffaele Zambrano

IPC: H01L021/00

CPC classification number: H01L27/11502 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/11507

Abstract: Presented is a memory cell integrated in a semiconductor substrate that includes a MOS device connected in series to a capacitive element. The MOS device has first and second conduction terminals, and the capacitive element has a lower electrode covered with a layer of a dielectric material and capacitively coupled to an upper electrode. The MOS device is overlaid by at least one metallization layer that is covered with at least one top insulating layer. The capacitive element is formed on the top insulating layer. The cell is unique in that the metallization layer extends only between the MOS device and the capacitive element.

Abstract translation: 提出了集成在半导体衬底中的存储单元，其包括与电容元件串联连接的MOS器件。 MOS器件具有第一和第二导电端子，并且电容元件具有被电介质材料层覆盖并且电容耦合到上电极的下电极。 MOS器件由被至少一个顶部绝缘层覆盖的至少一个金属化层覆盖。 电容元件形成在顶部绝缘层上。 该电池是唯一的，因为金属化层仅在MOS器件和电容元件之间延伸。

公开(公告)号：US20020041534A1

公开(公告)日：2002-04-11

申请号：US09919789

申请日：2001-07-31

Applicant: STMicroelectronics S.r.l.

Inventor： Roberto Gastaldi ,  Paolo Cappelletti ,  Giulio Casagrande ,  Giovanni Campardo ,  Rino Micheloni

IPC: G11C008/00

CPC classification number: G11C16/3431 ,  G11C16/16 ,  G11C16/34

Abstract: A semiconductor memory such as a flash memory, which comprises at least one two-dimensional array of memory cells with a plurality of rows and columns of memory cells grouped in a plurality of packets. The memory cells belonging to the columns of each packet are formed in a respective semiconductor region with a first type of conductivity, this region being distinct from the semiconductor regions with the first type of conductivity in which the memory cells belonging to the columns of the remaining packets are formed. The semiconductor regions with the first type of conductivity divide the set of memory cells belonging to each row into a plurality of subsets of memory cells that constitute elemental memory units which can be modified individually. Thus memory units of very small dimensions can be erased individually, without excessive overhead in terms of area.

Abstract translation: 诸如闪速存储器的半导体存储器，其包括具有分组在多个分组中的多个存储单元的行和列的存储器单元的至少一个二维阵列。 属于每个分组的列的存储单元形成在具有第一类型导电性的相应半导体区域中，该区域与具有第一类型导电性的半导体区域不同，其中存储单元属于剩余的列 形成包。 具有第一类型导电性的半导体区域将属于每一行的存储单元集合分成多个存储单元子集，这些存储单元子集构成可单独修改的元素存储单元。 因此，可以单独擦除非常小尺寸的存储单元，而在面积方面没有过多的开销。

公开(公告)号：US20040130000A1

公开(公告)日：2004-07-08

申请号：US10680721

申请日：2003-10-07

Applicant: STMicroelectronics S.r.l. ,  Ovonyx Inc.

Inventor： Fabio Pellizzer ,  Giulio Casagrande ,  Roberto Gastaldi ,  Loris Vendrame ,  Augusto Benvenuti ,  Tyler Lowrey

IPC: H01L027/082

CPC classification number: H01L29/685 ,  H01L27/101 ,  H01L27/24

Abstract: A process for manufacturing an array of cells, including: implanting, in a body of semiconductor material of a first conductivity type, a common conduction region of the first conductivity type; forming, in the body, above the common conduction region, a plurality of active area regions of a second conductivity type and a first doping level; forming, on top of the body, an insulating layer having first and second openings; implanting first portions of the active area regions through the first openings with a doping agent of the first conductivity type, thereby forming, in the active area regions, second conduction regions of the first conductivity type; implanting second portions of the active area regions through the second openings with a doping agent of the second conductivity type, thereby forming control contact regions of the second conductivity type and a second doping level, higher than the first doping level; forming, on top of the body, a plurality of storage components, each storage component having a terminal connected to a respective second conduction region.

Abstract translation: 一种用于制造单元阵列的方法，包括：在第一导电类型的半导体材料的主体中注入第一导电类型的共同导电区域; 在体内在公共导电区域上形成第二导电类型和第一掺杂水平的多个有源区域区域; 在所述主体的顶部上形成具有第一和第二开口的绝缘层; 通过第一导电类型的掺杂剂将有源区域的第一部分注入第一开口，从而在有源区域中形成第一导电类型的第二导电区域; 通过第二导电类型的掺杂剂将有源区域的第二部分注入第二开口，由此形成高于第一掺杂级的第二导电类型和第二掺杂级的控制接触区; 在主体的顶部上形成多个存储部件，每个存储部件具有连接到相应的第二传导区域的端子。

公开(公告)号：US20040150093A1

公开(公告)日：2004-08-05

申请号：US10680727

申请日：2003-10-07

Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

Inventor： Fabio Pellizzer ,  Giulio Casagrande ,  Roberto Bez

IPC: H01L023/48

CPC classification number: H01L27/2445 ,  H01L27/101 ,  H01L27/2463 ,  H01L29/685 ,  H01L45/06 ,  H01L45/1233

Abstract: A cell array is formed by a plurality of cells each including a selection bipolar transistor and a storage component. The cell array is formed in a body including a common collector region of P type; a plurality of base regions of N type, overlying the common collector region; a plurality of emitter regions of P type formed in the base regions; and a plurality of base contact regions of N type and a higher doping level than the base regions, formed in the base regions, wherein each base region is shared by at least two adjacent bipolar transistors.

Abstract translation: 单元阵列由多个单元形成，每个单元包括选择双极晶体管和存储组件。 电池阵列形成在包括P型共用集电极区域的主体中; 多个N型基极区，覆盖在公共集电极区域上; 在基区中形成多个P型发射极区; 以及形成在所述基极区域中的多个N型基极接触区域和比所述基极区域更高的掺杂水平的基极接触区域，其中每个基极区域由至少两个相邻的双极晶体管共享。