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公开(公告)号：US20220399880A1
公开(公告)日：2022-12-15
申请号：US17830864
申请日：2022-06-02
Applicant: STMicroelectronics S.r.l. , STMicroelectronics (Alps) SAS
Inventor： Antonino Conte , Marco Ruta , Michelangelo Pisasale , Thomas Jouanneau
Abstract: In an embodiment a ring oscillator circuit includes a chain of cascade-coupled inverter stages coupled between an oscillator supply voltage node and a reference voltage node, the oscillator supply voltage node configured to provide an oscillator supply voltage, a current generator circuit coupled between the oscillator supply voltage node and a system supply voltage node configured to provide a system supply voltage, the current generator circuit being configured to inject a current into the oscillator supply voltage node and a biasing circuit including a first bias control transistor and a second bias control transistor coupled in series between the reference voltage node and the oscillator supply voltage node, wherein the first bias control transistor is configured to selectively couple the reference voltage node and the oscillator supply voltage node in response to the oscillator control signal being indicative that the ring oscillator circuit is in an inactive operation state.
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公开(公告)号：US12212320B2
公开(公告)日：2025-01-28
申请号：US18296325
申请日：2023-04-05
Applicant: STMICROELECTRONICS S.r.l. , STMICROELECTRONICS (ALPS) SAS
Inventor： Antonino Conte , Marco Ruta , Michelangelo Pisasale , Thomas Jouanneau
IPC: H03K19/20 , H03K19/0185
Abstract: A level-shifter circuit receives one or more input signals in an input level domain and includes provides at an output node an output signal in an output level domain shifted with respect to the input level domain. The circuit includes output circuitry including a first drive node and a second drive node that receive first and second logical signals so that the output signal has a first output level or a second output level in the output level domain as a function of at least one of the first and second logical signals. The circuit includes first and second shift capacitors coupled to the first and second drive nodes as well as capacitor refresh circuitry.
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Patent Agency Ranking
公开(公告)号：US11641191B2
公开(公告)日：2023-05-02
申请号：US17830864
申请日：2022-06-02
Applicant: STMicroelectronics S.r.l. , STMicroelectronics (Alps) SAS
Inventor： Antonino Conte , Marco Ruta , Michelangelo Pisasale , Thomas Jouanneau
Abstract: In an embodiment a ring oscillator circuit includes a chain of cascade-coupled inverter stages coupled between an oscillator supply voltage node and a reference voltage node, the oscillator supply voltage node configured to provide an oscillator supply voltage, a current generator circuit coupled between the oscillator supply voltage node and a system supply voltage node configured to provide a system supply voltage, the current generator circuit being configured to inject a current into the oscillator supply voltage node and a biasing circuit including a first bias control transistor and a second bias control transistor coupled in series between the reference voltage node and the oscillator supply voltage node, wherein the first bias control transistor is configured to selectively couple the reference voltage node and the oscillator supply voltage node in response to the oscillator control signal being indicative that the ring oscillator circuit is in an inactive operation state.
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公开(公告)号：US11996849B2
公开(公告)日：2024-05-28
申请号：US18176753
申请日：2023-03-01
Applicant: STMicroelectronics (Alps) SAS
Inventor： Thomas Jouanneau
CPC classification number: H03K5/15066 , H03K5/15093 , H03L7/0996
Abstract: In accordance with an embodiment, a timing sequence generation circuit includes: a ring oscillator having a plurality of clock signal outputs configured to provide clock signals delayed in time with respect to one another; a first shift register comprising a flip-flop having a clock input coupled to a clock signal input of the first shift register and an output coupled to an output of the first shift register; and a first circuit configured to: select a clock signal from among the clock signals; and deliver the selected clock signal to the clock signal input of the first shift register
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公开(公告)号：US20230291395A1
公开(公告)日：2023-09-14
申请号：US18176753
申请日：2023-03-01
Applicant: STMicroelectronics (Alps) SAS
Inventor： Thomas Jouanneau
CPC classification number: H03K5/15066 , H03K5/15093 , H03L7/0996
Abstract: In accordance with an embodiment, a timing sequence generation circuit includes: a ring oscillator having a plurality of clock signal outputs configured to provide clock signals delayed in time with respect to one another; a first shift register comprising a flip-flop having a clock input coupled to a clock signal input of the first shift register and an output coupled to an output of the first shift register; and a first circuit configured to: select a clock signal from among the clock signals; and deliver the selected clock signal to the clock signal input of the first shift register
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公开(公告)号：US20210367518A1
公开(公告)日：2021-11-25
申请号：US17324782
申请日：2021-05-19
Applicant: STMicroelectronics (Alps) SAS
Inventor： Thomas Jouanneau
Abstract: The integrated circuit includes a first node intended to be biased at a first voltage, a second node intended to be biased at a second voltage and having a non-negligible capacitive coupling with the first node. A power supply management device comprises a voltage booster configured to boost a power supply voltage and comprising boost stages configured to generate intermediate voltages on intermediate nodes. A compatibility detection circuit is configured to detect compatibility between the second voltage and one of the intermediate voltages, and, if the second voltage is compatible with an intermediate voltage, to couple the at least one second node to the compatible intermediate node.
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公开(公告)号：US11469671B2
公开(公告)日：2022-10-11
申请号：US17324782
申请日：2021-05-19
Applicant: STMicroelectronics (Alps) SAS
Inventor： Thomas Jouanneau
Abstract: The integrated circuit includes a first node intended to be biased at a first voltage, a second node intended to be biased at a second voltage and having a non-negligible capacitive coupling with the first node. A power supply management device comprises a voltage booster configured to boost a power supply voltage and comprising boost stages configured to generate intermediate voltages on intermediate nodes. A compatibility detection circuit is configured to detect compatibility between the second voltage and one of the intermediate voltages, and, if the second voltage is compatible with an intermediate voltage, to couple the at least one second node to the compatible intermediate node.
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