公开(公告)号：US20240178849A1

公开(公告)日：2024-05-30

申请号：US18434225

申请日：2024-02-06

Applicant: Marvell Asia Pte., Ltd.

Inventor： Eitan Rosen ,  Oded Norman

IPC: H03L7/16 ,  H03K3/03 ,  H03K5/13 ,  H03L5/00 ,  H03L7/099

CPC classification number: H03L7/16 ,  H03K3/0315 ,  H03K5/13 ,  H03L5/00 ,  H03L7/0995 ,  H03L7/0996

Abstract: A circuit and corresponding method control cycle time of an output clock used to clock at least one other circuit. The circuit comprises an agile ring oscillator (ARO) and ARO controller. The ARO includes at least one instance of a first ring oscillator (RO) and second RO that generate high and low phases, respectively, of cycles of the output clock. The ARO controller controls durations of the high and low phases, independently, via first and second control words output to the ARO, respectively. In a present cycle of the output clock, the ARO controller effects a change to the high or low phase, or a combination thereof, in a next cycle of the output clock by updating the first or second control word, or a combination thereof, based on an indication of expected usage of the at least one other circuit in the next cycle. The change improves a performance-to-power ratio of the at least one other circuit.

公开(公告)号：US20180323792A1

公开(公告)日：2018-11-08

申请号：US15586867

申请日：2017-05-04

Applicant: Cavium, Inc.

Inventor： JingDong Deng ,  Omer O. Yildirim

IPC: H03L7/193 ,  H03K3/356 ,  H03K23/44 ,  H03L7/099 ,  H03L7/089 ,  H03L7/081 ,  H03K3/3562

CPC classification number: H03L7/193 ,  H03K3/356139 ,  H03K3/35625 ,  H03K23/425 ,  H03K23/44 ,  H03L7/081 ,  H03L7/0891 ,  H03L7/0996

Abstract: A frequency divider circuit comprises a first divider chain including at least one first divider cell and a second divider chain coupled to the first divider chain to form an extendable divider chain. The second divider chain includes at least one second divider cell with a respective reset control. An effective length of the extendable divider chain may be altered, dynamically, via the respective reset control. Altering the effective length, dynamically, enables a division ratio of the frequency divider circuit to be changed, dynamically. The frequency divider circuit may be advantageously employed by applications that rely upon a dynamic division ratio, such as a fractional-N (frac-N) phase-locked loop (PLL).

公开(公告)号：US20180159546A1

公开(公告)日：2018-06-07

申请号：US15577930

申请日：2015-06-16

Applicant: Telefonaktiebolaget LM Ericsson (publ)

Inventor： Staffan Ek ,  Tony Påhlsson ,  Henrik Sjöland

IPC: H03L7/099 ,  H03L7/191 ,  H03L7/197

CPC classification number: H03L7/0996 ,  H03K23/667 ,  H03K23/68 ,  H03L7/191 ,  H03L7/1974

Abstract: An electronic circuit arranged to receive an oscillating signal and output an output signal at a frequency having a frequency relation with the oscillating signal defined by a divide ratio is provided. The electronic circuit comprises a first frequency divider arranged to receive the oscillating signal and output N frequency divided signals of different phases, a second frequency divider arranged to receive one of the N signals and frequency divide the received signal by a value given by a first control signal provided to the second frequency divider, N latch circuits each being arranged to receive a respective one of the N signals at a clocking input of the respective latch circuit and to receive an output of the second frequency divider at an input of the respective latch circuit, a multiplexer circuit arranged to receive outputs of the N latch circuits and to output a signal, on which the output signal is based, selected from the received signals based on a second control signal provided to the multiplexer circuit, and a control circuit arranged to provide the first control signal and the second control signal based on the divide ratio. A phase-locked loop circuit, a transceiver circuit, a radio station, and a method of frequency dividing an oscillating signal are also provided.

公开(公告)号：US20180097521A1

公开(公告)日：2018-04-05

申请号：US15676080

申请日：2017-08-14

Applicant: Apple Inc.

Inventor： Joachim S. Hammerschmidt ,  Robert G. Lorenz

IPC: H03L7/089 ,  H03C3/09 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18

CPC classification number: H03L7/0893 ,  H03B5/1243 ,  H03B5/1265 ,  H03B2201/025 ,  H03B2201/0266 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/095 ,  H03C3/0958 ,  H03C3/0991 ,  H03J2200/10 ,  H03L7/0805 ,  H03L7/0996 ,  H03L7/104 ,  H03L7/105 ,  H03L7/18 ,  H03L7/189 ,  H03L2207/06

Abstract: A method and apparatus for performing a two-point calibration of a VCO in a PLL is disclosed. The method includes determining a first steady state tuning voltage of the VCO with no modulation voltage applied. Thereafter, an iterative process may be performed wherein a modulation voltage is applied to the VCO (along with the tuning voltage) and a modified divisor is applied to the divider circuit in the feedback loop. During each iteration, after the PLL is settled, the tuning voltage is measured and a difference between the current value and the first value is determined. If the current and first values of the turning voltage are not equal, another iteration may be performed, modifying at least one of the modulation voltage and the divisor, and determining the difference between the current and first values of the tuning voltage.

公开(公告)号：US20180034468A1

公开(公告)日：2018-02-01

申请号：US15224224

申请日：2016-07-29

Applicant: Movellus Circuits, Inc.

Inventor： Muhammad Faisal ,  Jeffrey Alan Fredenburg

IPC: H03L7/099 ,  H03L7/08 ,  H04L27/152 ,  H03L7/081

CPC classification number: H03L7/0997 ,  H03L7/0802 ,  H03L7/081 ,  H03L7/0996 ,  H03L7/0998 ,  H03L2207/50 ,  H04L27/0014 ,  H04L27/152

Abstract: A reconfigurable frequency and delay generator is disclosed, and a representative embodiment may include a phase sampler and plurality of configurable oscillator stages, each configurable oscillator stage of the plurality of configurable oscillator stages comprising: a plurality of core inverters coupled in series, a last core inverter of the plurality of core inverters generating an output signal having a configurable output frequency; and a plurality of delay control circuits, each delay control circuit of the plurality of delay control circuits coupled to an output of a corresponding core inverter of the plurality of core inverters.

公开(公告)号：US08729944B2

公开(公告)日：2014-05-20

申请号：US13333011

申请日：2011-12-21

Applicant: Bruce A. Doyle ,  Emerson S. Fang ,  Alvin L. Loke ,  Shawn Searles ,  Stephen F. Greenwood

Inventor： Bruce A. Doyle ,  Emerson S. Fang ,  Alvin L. Loke ,  Shawn Searles ,  Stephen F. Greenwood

IPC: H03K5/13

CPC classification number: H03K3/0322 ,  H03L7/0996

Abstract: A device may include first, second, and third buffer stages. The device may further include a selector circuit to selectively output one of an output of the second buffer stage or an output of the third buffer stage. The device may include an output to provide a first clock signal, where the first clock signal is an output of the first buffer stage, and the device further include an output to provide a second clock signal, where the second clock signal is an output of the selector circuit.

Abstract translation: 装置可以包括第一，第二和第三缓冲级。 该装置还可以包括选择器电路，用于选择性地输出第二缓冲级的输出或第三缓冲级的输出之一。 器件可以包括输出以提供第一时钟信号，其中第一时钟信号是第一缓冲器级的输出，并且器件还包括输出以提供第二时钟信号，其中第二时钟信号是 选择器电路。

公开(公告)号：US08582708B2

公开(公告)日：2013-11-12

申请号：US13344201

申请日：2012-01-05

Applicant: Michiyo Yamamoto ,  Kenji Murata ,  Kazuya Hatooka

Inventor： Michiyo Yamamoto ,  Kenji Murata ,  Kazuya Hatooka

IPC: H04L7/00

CPC classification number: H04L7/0337 ,  H03L7/091 ,  H03L7/0996

Abstract: A clock and data recovery circuit includes a multiphase clock generator circuit which generates a multiphase clock having a plurality of clocks, a sampling circuit which samples a received data signal transferring serial data in synchronism with each of the plurality of clocks, and generates a plurality of data signals, a data recovery unit which generates a selection signal indicating a data signal having an appropriate phase among the plurality of data signals, and a storage unit which stores the selection signal. The data recovery unit selects one of the plurality of data signals, based on the selection signal read from the storage unit, and a clock corresponding to the selected data signal.

Abstract translation: 时钟和数据恢复电路包括产生具有多个时钟的多相时钟的多相时钟发生器电路，采样电路，对与多个时钟中的每个时钟同步地传送串行数据的接收数据信号进行采样，并产生多个 数据信号，数据恢复单元，其生成指示在多个数据信号中具有适当相位的数据信号的选择信号;以及存储单元，存储选择信号。 数据恢复单元基于从存储单元读取的选择信号和对应于所选择的数据信号的时钟来选择多个数据信号中的一个。

公开(公告)号：US08552787B2

公开(公告)日：2013-10-08

申请号：US12813386

申请日：2010-06-10

Applicant: Koushik Krishnan ,  Jafar Savoj

Inventor： Koushik Krishnan ,  Jafar Savoj

IPC: H03K3/00

CPC classification number: H03L7/0996 ,  H03K23/005 ,  H03K23/68

Abstract: Methods and apparatus for a gray-coded phase rotating frequency divider. A phase selector is provided that includes two or more selectors, each selector configured to receive multiple clock phases and output a respective clock phase based on one or more selection bits that are part of a selection input, and a gray code generator configured to generate a gray coded output that forms the selection input so that when the gray coded output changes state only selection bits associated with a single selector change. A method includes grouping a plurality of clock phases into two or more groups, for each group, selecting a respective clock phase based on one or more selection bits that are part of a selection input, and generating a gray coded output that forms the selection input so that when the gray coded output changes state only selection bits associated with a single group change.

Abstract translation: 灰色相位旋转分频器的方法和装置。 提供一种相位选择器，其包括两个或多个选择器，每个选择器被配置为接收多个时钟相位，并且基于作为选择输入的一部分的一个或多个选择位输出相应的时钟相位;以及灰色代码生成器， 灰色编码输出形成选择输入，使得当灰度编码输出仅改变与单个选择器改变相关联的选择位的状态。 一种方法包括对于每个组将多个时钟相位分成两组或多组，基于作为选择输入的一部分的一个或多个选择位选择相应的时钟相位，并且生成形成选择输入的灰度编码输出 使得当灰度编码输出仅改变与单个组相关联的选择位的状态改变时。

公开(公告)号：US08165199B2

公开(公告)日：2012-04-24

申请号：US12254381

申请日：2008-10-20

Applicant: Liming Xiu ,  Grady Cook ,  Daniel Dudek ,  Hongbing Lian ,  Yihe Hu ,  Christopher S. Tracy

Inventor： Liming Xiu ,  Grady Cook ,  Daniel Dudek ,  Hongbing Lian ,  Yihe Hu ,  Christopher S. Tracy

IPC: G06F1/04 ,  H03D3/24

CPC classification number: H04N21/4305 ,  H03L7/0996 ,  H03L7/18 ,  H04N21/42615 ,  H04N21/434

Abstract: This invention uses a flying adder frequency synthesis circuit to provide the required frequency adjustments to accommodate the varying encoding density of a MPEG2 video data stream. This invention adjusts the local clock based on the information extracted from the program clock reference signal in the incoming data. This invention replaces an external or internal voltage-controlled crystal oscillator using a phase locked loop circuit on the video processing integrated circuit.

Abstract translation: 本发明使用飞行加法器频率合成电路来提供所需的频率调整以适应MPEG2视频数据流的变化的编码密度。 本发明基于从输入数据中的节目时钟参考信号中提取的信息来调整本地时钟。 本发明使用视频处理集成电路上的锁相环电路代替外部或内部压控晶体振荡器。

公开(公告)号：US20120025918A1

公开(公告)日：2012-02-02

申请号：US13170187

申请日：2011-06-28

Applicant: Chi-Hsueh Wang ,  Robert Bogdan Staszewski

Inventor： Chi-Hsueh Wang ,  Robert Bogdan Staszewski

IPC: H03L7/06

CPC classification number: H03L7/0996

Abstract: An exemplary calibration apparatus for calibrating timing mismatch of an edge rotator operating on multiple phases of an oscillator includes a capturing block arranged to capture phase error samples, and a calibrating block arranged to adjust timing of said edge rotator according to said phase error samples. An exemplary calibration method for calibrating timing mismatch of an edge rotator operating on multiple phases of an oscillator includes the following steps: capturing phase error samples, and adjusting timing of said edge rotator according to said phase error samples.

Abstract translation: 用于校准在振荡器的多相上操作的边缘旋转器的定时失配的示例性校准装置包括布置成捕获相位误差采样的捕获块，以及被配置为根据所述相位误差样本调整所述边缘旋转器的定时的校准块。 用于校准在振荡器的多相上操作的边缘旋转器的定时失配的示例性校准方法包括以下步骤：捕获相位误差样本，并根据所述相位误差样本调整所述边缘旋转器的定时。