INTEGRATED COMPARATOR WITH HYSTERESIS, IN PARTICULAR PRODUCED IN AN FD SOI TECHNOLOGY
    1.
    发明申请
    INTEGRATED COMPARATOR WITH HYSTERESIS, IN PARTICULAR PRODUCED IN AN FD SOI TECHNOLOGY 审中-公开
    具有HYSTERESIS的集成比较器,特别是在FD SOI技术中生产

    公开(公告)号:US20140091846A1

    公开(公告)日:2014-04-03

    申请号:US14040781

    申请日:2013-09-30

    Inventor: Francois Agut

    CPC classification number: H03K3/3565 H03K3/02337

    Abstract: A comparator circuit includes an input differential amplifier circuit generating an output signal and an inverting output circuit generating a complemented output signal. The differential amplifier circuit is formed of a differential pair of input transistors and a pair of diode connected load transistors. The comparator circuit is integrated in a silicon on insulator type structure. A hysteresis-creating circuit is formed by coupling one or more of the output signal and complemented output signal to a substrate region (in the silicon on insulator type structure) associated with one or more of the differential pair of input transistors and pair of diode connected load transistors. The differential amplifier circuit may further include auxiliary transistors coupled to the diode connected load transistors and the hysteresis-creating circuit may further couple one or more of the output signal and complemented output signal to the substrate region associated with the auxiliary transistor.

    Abstract translation: 比较器电路包括产生输出信号的输入差分放大器电路和产生补码输出信号的反相输出电路。 差分放大器电路由差分输入晶体管和一对二极管连接的负载晶体管组成。 比较器电路集成在绝缘体上的绝缘体结构中。 通过将输出信号和补充输出信号中的一个或多个耦合到与一个或多个差分输入晶体管和二极管连接的一个或多个的衬底区域(在绝缘体上的绝缘体结构中)形成磁滞产生电路 负载晶体管。 差分放大器电路还可以包括耦合到二极管连接的负载晶体管的辅助晶体管,并且产生滞后的电路还可将输出信号和补码输出信号中的一个或多个耦合到与辅助晶体管相关联的衬底区域。

    Switched-mode power converter
    2.
    发明授权

    公开(公告)号:US10862395B2

    公开(公告)日:2020-12-08

    申请号:US16437923

    申请日:2019-06-11

    Abstract: A switched-mode power converter device includes an inductive element coupling a first node receiving an input voltage to a second node. A first transistor couples the second node to a third node generating an output voltage. A control circuit includes a first switch coupling the third node to a control terminal of the first transistor.

    IMAGE SENSOR
    3.
    发明申请

    公开(公告)号:US20220272291A1

    公开(公告)日:2022-08-25

    申请号:US17667485

    申请日:2022-02-08

    Abstract: The present description describes an image sensor including an array of pixels arranged inside and on top of a region of a semiconductor substrate electrically insulated from the rest of the substrate by insulating trenches crossing the substrate, each pixel including a photoconversion area and at least two assemblies, each including a memory area and a transfer gate coupling the memory area to the photoconversion area, and a circuit configured to apply, for each pixel and at least during each integration phase, a bias voltage different from ground to a portion of the substrate having the pixel arranged inside and on top of it.

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