公开(公告)号：US20230229407A1

公开(公告)日：2023-07-20

申请号：US18099214

申请日：2023-01-19

Applicant: SambaNova Systems, Inc.

Inventor： Raghu PRABHAKAR ,  David Brian JACKSON ,  Scott BURSON

IPC: G06F8/41 ,  G06F9/445

CPC classification number: G06F8/441 ,  G06F9/44505

Abstract: A complier produces a configuration file to configure a fracturable data path of a configurable unit in a coarse-grained reconfigurable processor to concurrently generate different address sequences generated using different address associated with different operations. The fracturable data path includes multiple computation stages respectively including a pipeline register. The compiler analyzes a first address calculation and a second address calculation and assigns a first set of stages to the first operation to generate the first address sequence and a second set of stages to the second operation to generate the second address sequence using the second set of stages, based on the analysis. A configuration file for the configurable unit is generated by the compiler that assigns the first set of stages to the first operation and the second set of stages to the second operation and includes two or more immediate values for each computation stage.

公开(公告)号：US20240192935A1

公开(公告)日：2024-06-13

申请号：US18583845

申请日：2024-02-21

Applicant: SambaNova Systems, Inc.

Inventor： Raghu PRABHAKAR ,  David Brian JACKSON ,  Scott BURSON

IPC: G06F8/41 ,  G06F9/30 ,  G06F9/445 ,  G06F15/80

CPC classification number: G06F8/441 ,  G06F9/3001 ,  G06F9/44505 ,  G06F15/80

Abstract: A compiler generates a configuration file to configure a fracturable data path in a coarse-grained reconfigurable processor. The configuration file, when loaded into the reconfigurable processor enables a fracturable data path in a configurable unit of the reconfigurable processor to produce multiple independent address sequences by analyzing two address calculations to determine the number of pipeline stages for each calculation. The configuration file includes first and second configuration data for distinct sets of computational stages within the pipelined computation stages, allowing the processor to generate a first address sequence using N pipeline stages and a second address sequence using M pipeline stages, where N and M are positive integers.