公开(公告)号：US20230385028A1

公开(公告)日：2023-11-30

申请号：US17664835

申请日：2022-05-24

申请人： Oracle International Corporation

发明人： Mario Wolczko

IPC分类号： G06F8/20 ,  G06F8/41 ,  G06F9/455

CPC分类号： G06F8/24 ,  G06F8/436 ,  G06F8/441 ,  G06F9/4552

摘要： Systems, computer instructions and computer-implemented methods are disclosed for implementing space- and time-efficient enumerations. An instance of an enumeration class may be created with a constant, plurality of enumerations. A plurality of objects corresponding to the respective enumerations may be stored in memory along with a lookup table indexed by respective ordinal values of the plurality of enumerations, the lookup table including respective references to the stored objects of the instantiated enumeration class. A reference to an enumeration may be stored in a memory location by storing an ordinal value of the enumeration. A determination may then be made to convert a stored ordinal value to a reference to an object, and responsive to the determination, the ordinal value may be loaded and used as an index into the lookup table to obtain the reference to the object corresponding to the enumeration.

公开(公告)号：US11797274B2

公开(公告)日：2023-10-24

申请号：US17353898

申请日：2021-06-22

申请人： Altered State Machine Limited

发明人： David McDonald

IPC分类号： G06F8/35 ,  G06F8/41 ,  H04L9/32 ,  A63F13/77 ,  G06N20/00 ,  H04L9/00

CPC分类号： G06F8/35 ,  A63F13/77 ,  G06F8/441 ,  G06N20/00 ,  H04L9/3213 ,  H04L9/50

摘要： Disclosed implementations provide executable models, such as artificial intelligence models that can be owned, traded, and used in various execution environments. By coupling a model with a strictly defined interface definition, the model can be executed in various execution environments that support the interface. Coupling the model with a non-fungible cryptographic token allows the model and other components to be owned and traded as a unit. The tradeable composite units have utility across multiple supported execution environments, such as video game environments, chat bot environments and financial trading environments. Additionally, the interface allows for the creation of pipelines and systems from multiple complementary composite units.

公开(公告)号：US11656854B2

公开(公告)日：2023-05-23

申请号：US17460749

申请日：2021-08-30

申请人： HUAWEI TECHNOLOGIES CO., LTD.

发明人： Xun Deng ,  Kai-Ting Amy Wang

IPC分类号： G06F8/41 ,  G06F8/30

CPC分类号： G06F8/441 ,  G06F8/37 ,  G06F8/433 ,  G06F8/452 ,  G06F8/457

摘要： There is provided methods and devices for computing a tile size for software optimization. A method includes receiving, by a computing device, information indicative of one or more of a set of loop bounds and a set of data shapes; processing, by the computing device, the information to determine a computation configuration based on the obtained information, the computation configuration implementable by a compiler, said processing including evaluating at least the computation configuration based on a build cost model, the build cost model representative of a data transfer cost and a data efficiency of the computation configuration; and transmitting, by the computing device, instructions directing the compiler to implement the computation configuration.

公开(公告)号：US20190220281A1

公开(公告)日：2019-07-18

申请号：US16363018

申请日：2019-03-25

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Michael K. Gschwind

IPC分类号： G06F9/30 ,  G06F9/34

CPC分类号： G06F9/30189 ,  G06F8/434 ,  G06F8/441 ,  G06F8/447 ,  G06F9/342

摘要： A short pointer mode application is loaded in an address space configured for use by a plurality of types of applications including the short pointer mode application and a long pointer mode application. The address space has a first portion addressable by short pointers of a defined size and a second portion addressable by long pointers of another defined size. The other defined size is different from the defined size. Based on executing the short pointer mode application, one or more short pointers of the short pointer mode application are converted to one or more long pointers; and the one or more long pointers are used to access memory within the first portion of the address space addressable by short pointers.

公开(公告)号：US20180082397A1

公开(公告)日：2018-03-22

申请号：US15270648

申请日：2016-09-20

申请人： Intel Corporation

发明人： Konstantin S. Bobrovsky ,  Serguei N. Dmitriev ,  Knud J. Kirkegaard

IPC分类号： G06T1/20 ,  G06T1/60 ,  G06F15/82

CPC分类号： G06T1/20 ,  G06F8/441 ,  G06F8/54 ,  G06F9/544 ,  G06F9/547 ,  G06F15/82 ,  G06F2209/509 ,  G06T1/60 ,  G06T15/005 ,  G06T17/20

摘要： A processing apparatus is described. The apparatus includes a central processing unit (CPU), a graphics processing unit (GPU) and data sharing logic to perform static physical data sharing between the CPU and the GPU by changing code written for the GPU to operate with CPU variables.

公开(公告)号：US20180081819A1

公开(公告)日：2018-03-22

申请号：US15828799

申请日：2017-12-01

申请人： Renesas Electronics Corporation

发明人： Katsunori TANAKA

IPC分类号： G06F9/45

CPC分类号： G06F12/0897 ,  G06F8/41 ,  G06F8/434 ,  G06F8/441 ,  G06F8/447 ,  G06F2212/1016

摘要： A data processing method for a data processing device, the data processing device including: a program execution unit comprising a processor, and memories on a plurality of layers; an arithmetic control unit that receives a program and attribute values, the program including a plurality of subroutines for causing the processor to read a read block from the memory, perform data processing, and write a write block to the memory, the write block being a result of the data processing, the attribute values being set for the read block and the write block, respectively; and a memory access monitoring unit.

公开(公告)号：US09836408B2

公开(公告)日：2017-12-05

申请号：US14885830

申请日：2015-10-16

申请人： Renesas Electronics Corporation

发明人： Katsunori Tanaka

IPC分类号： G06F12/08 ,  G06F9/45 ,  G06F12/0897

CPC分类号： G06F12/0897 ,  G06F8/41 ,  G06F8/434 ,  G06F8/441 ,  G06F8/447 ,  G06F2212/1016

摘要： A data processing method, a computer readable medium, and a data processing device capable of improving processing efficiency are provided. A storage destination of sub-read blocks is changed to a high-speed small-capacity memory on a high layer by adding a shape attribute in an attribute group for data blocks, adding a memory access monitoring unit for obtaining the shape attribute of a data block to the configuration of a data processing device, obtaining the shape attribute of the non-rectangular read block by executing a program on a trial basis, and propagating this shape attribute in a direction opposite to a data flow or a process flow within the program.

公开(公告)号：US09785423B2

公开(公告)日：2017-10-10

申请号：US14694856

申请日：2015-04-23

申请人： Google Inc.

发明人： Albert Meixner

IPC分类号： G06K9/00 ,  G06F15/80 ,  G06F9/45 ,  G06F9/30

CPC分类号： G06F8/451 ,  G06F8/441 ,  G06F8/4441 ,  G06F8/445 ,  G06F9/30003 ,  G06F9/3001 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30134 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/3887

摘要： A method is described that includes translating higher level program code including higher level instructions having an instruction format that identifies pixels to be accessed from a memory with first and second coordinates from an orthogonal coordinate system into lower level instructions that target a hardware architecture having an array of execution lanes and a shift register array structure that is able to shift data along two different axis. The translating includes replacing the higher level instructions having the instruction format with lower level shift instructions that shift data within the shift register array structure.

公开(公告)号：US09696975B2

公开(公告)日：2017-07-04

申请号：US12875753

申请日：2010-09-03

申请人： David P. Belanger ,  Christopher A. Lapkowski ,  Chwan-Hang Lee

发明人： David P. Belanger ,  Christopher A. Lapkowski ,  Chwan-Hang Lee

IPC分类号： G06F9/45

CPC分类号： G06F8/441

摘要： Register halves are allocated independently when performing register allocation during program compilation, thereby effectively doubling the number of registers which are available for allocation, which in turn may reduce spill code and improve run-time performance. When hardware registers are 64 bits wide, for example, an architecture supporting the present invention provides some number of separate hardware instructions that operate on the 32-bit high-word and/or the 32-bit low word of the hardware registers as if those 32-bit words are separate registers. Such hardware instructions are able to manipulate the register halves independently, leaving the other register half untouched. A register coloring algorithm using in the compilation process is invoked using the number of register halves, instead of the number of hardware registers.

公开(公告)号：US20170154405A1

公开(公告)日：2017-06-01

申请号：US15431990

申请日：2017-02-14

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： LIANGLIANG CAO ,  LIANA L. FONG ,  WEI TAN

IPC分类号： G06T1/60 ,  G06F12/0877 ,  G06T1/20 ,  G06F17/16

CPC分类号： G06T1/60 ,  G06F3/0601 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G06F8/441 ,  G06F8/443 ,  G06F8/453 ,  G06F12/0813 ,  G06F12/0875 ,  G06F12/0877 ,  G06F13/16 ,  G06F17/16 ,  G06F2212/1024 ,  G06F2212/302 ,  G06F2212/454 ,  G06F2212/455 ,  G06F2212/60 ,  G06F2212/656 ,  H03M13/6566

摘要： Embodiments include method, systems and computer program products for performing memory-aware matrix factorization on a graphics processing unit. Aspects include determining one or more types of memory on the graphics processing unit and determining one or more characteristics of each of the one or more types of memory. Aspects also include assigning each of a plurality of memory accesses of a matrix factorization algorithm to one of the one or more types of memory based on the one or more characteristics and executing the matrix factorization algorithm on the graphics processing unit.