公开(公告)号：US12027098B2

公开(公告)日：2024-07-02

申请号：US18227187

申请日：2023-07-27

Applicant: Samsung Display Co., LTD.

Inventor： Hyunsu Kim ,  Jundal Kim ,  Kyungyoul Min ,  Jongman Bae

IPC: G09G3/20 ,  G09G3/32

CPC classification number: G09G3/2092 ,  G09G3/32 ,  G09G2310/061 ,  G09G2310/08 ,  G09G2320/0233 ,  G09G2330/023 ,  G09G2340/0435

Abstract: A display device includes a driving controller, a display panel, and an emission driver. The driving controller generates a second clock signal having second pulses in response to a first clock signal having first pulses from an external device. The display panel includes pixels. The emission driver generates an emission signal having third pulses in response to the second clock signal and applies the emission signal to the pixels. The driving controller compares a number of the first pulses and a number of the second pulses, with a first reference value, and a second reference value, and sets a compensation value of the number of the second pulses, and the driving controller compensates for the second clock signal by adjusting the number of the second pulses existing in one horizontal time based on the compensation value in a vertical blank period of the frame period.

公开(公告)号：US12190845B2

公开(公告)日：2025-01-07

申请号：US18081062

申请日：2022-12-14

Applicant: Samsung Display Co., Ltd.

Inventor： Jongman Bae ,  Jundal Kim ,  Hyunsu Kim ,  Dong-Won Park ,  Junyong Song ,  Taeyoung Jin

IPC: H03L7/07 ,  G09G5/00

Abstract: An electronic device includes a host processor including a data transmitter, a driving driver, and a display panel. The data transmitter includes a phase locked loop that generates a first clock and a second clock, a clock block that receives the first clock, a plurality of data blocks that receives the second clock, a first buffer connected between the phase locked loop and the clock block, and a plurality of second buffers respectively connected between the phase locked loop and the plurality of data blocks, and the first buffer and each of the plurality of second buffers may be activated or deactivated depending on an interface mode.

公开(公告)号：US20240428721A1

公开(公告)日：2024-12-26

申请号：US18603344

申请日：2024-03-13

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Hyunsu Kim ,  Jongman Bae

IPC: G09G3/20

Abstract: An electronic device including: a host processor to generate a first clock signal and to output frame data and a synchronization signal; a driving controller to receive the synchronization signal and the frame data from the host processor and to generate a control signal based on a second clock signal; and a display panel, wherein the driving controller synchronizes the second clock signal with the first clock signal based on the synchronization signal, wherein the driving controller includes an error detector to detect an error of the synchronization signal, and wherein the error detector outputs a first signal when the error is an initial synchronization fail error and outputs a second signal different from the first signal when the error is a synchronization loss error.