公开(公告)号：US20240260356A1

公开(公告)日：2024-08-01

申请号：US18496918

申请日：2023-10-30

Applicant: Samsung Display Co., LTD.

Inventor： SANG-UK LIM ,  HYUK KIM ,  SEUNGSOO BAEK ,  DOO-YOUNG LEE ,  BOYONG CHUNG

IPC: H10K59/131 ,  G09G3/3233 ,  H10K59/121

CPC classification number: H10K59/131 ,  G09G3/3233 ,  H10K59/1216 ,  G09G2300/0819 ,  G09G2300/0852

Abstract: A display device includes a first conductive layer disposed on a substrate and including a capacitor electrode, an active layer disposed on the first conductive layer and including a switching active pattern, the switching active pattern at least partially overlapping the capacitor electrode in a plan view and constituting a storage capacitor together with the capacitor electrode, a second conductive layer disposed on the active layer, a pixel electrode layer disposed on the second conductive layer and including a pixel electrode, the pixel electrode including a first part spaced apart from the switching active pattern in the plan view and a second part extending from the first part and overlapping the switching active pattern in the plan view, and a light emitting layer disposed on the pixel electrode layer.

公开(公告)号：US20240265872A1

公开(公告)日：2024-08-08

申请号：US18507102

申请日：2023-11-13

Applicant: Samsung Display Co., Ltd.

Inventor： BOGYEONG KIM ,  DOO-YOUNG LEE ,  TAK-YOUNG LEE ,  BOYONG CHUNG ,  BYUNGSEOK CHOI

IPC: G09G3/3258 ,  H10K59/121 ,  H10K59/131

CPC classification number: G09G3/3258 ,  H10K59/121 ,  H10K59/131 ,  G09G2300/0426 ,  G09G2300/0842

Abstract: A display device includes a substrate, a first conductive layer disposed on the substrate, a second conductive layer disposed on the first conductive layer and a third conductive layer disposed on the second conductive layer. The first conductive layer includes a data line extending in a first direction. The second conductive layer includes a first scan line extending in a second direction intersecting the first direction, and a second scan line spaced apart from the first scan line and extending in the second direction. The third conductive layer includes a first driving voltage line extending in the second direction, a first common voltage line spaced apart from the first driving voltage line and extending in the second direction, and a pixel electrode disposed between the first driving voltage line and the first common voltage line in a plan view.

公开(公告)号：US20240096283A1

公开(公告)日：2024-03-21

申请号：US18197988

申请日：2023-05-16

Applicant: Samsung Display Co., LTD.

Inventor： SANG-UK LIM ,  JONGHEE KIM ,  HYUK KIM ,  SEUNGHYUN PARK ,  DOO-YOUNG LEE ,  BOYONG CHUNG

IPC: G09G3/3258 ,  G09G3/20 ,  G09G3/3233 ,  G09G3/3275

CPC classification number: G09G3/3258 ,  G09G3/2096 ,  G09G3/3233 ,  G09G3/3275 ,  G09G2300/0842 ,  G09G2310/08 ,  G09G2320/0233 ,  G09G2320/0257 ,  G09G2320/045 ,  G09G2330/021 ,  G09G2330/028

Abstract: A display device includes a display panel including pixels, a gate driver which sequentially applies scan signals to pixel rows including the pixels at a scan frequency, a data driver which applies data voltages to the pixels, a power voltage generator which applies a power voltage to the pixels, and a timing controller which sets a ripple frequency of the power voltage to deviate from the scan frequency by a predetermined reference ratio or more.

公开(公告)号：US20230269984A1

公开(公告)日：2023-08-24

申请号：US18111998

申请日：2023-02-21

Applicant: Samsung Display Co., Ltd.

Inventor： DOO-YOUNG LEE ,  BOGYEONG KIM ,  TAK-YOUNG LEE ,  SANG-UK LIM

IPC: H10K59/131

CPC classification number: H10K59/1315

Abstract: A display panel includes a base layer, a first conductive layer disposed on the base layer and including a power pattern, a second conductive layer disposed on the first conductive layer, and a first insulating layer disposed between the first conductive layer and the second conductive layer. The first insulating layer is provided with at least one first contact hole defined therethrough and disposed at an upper side in a plan view and at least one second contact hole defined therethrough and disposed at a lower side in a plan view, the first conductive layer is electrically connected to the second conductive layer via the at least one first contact hole and the at least one second contact hole, and a number of the at least one first contact hole is equal to a number of the at least one second contact hole.

公开(公告)号：US20240395191A1

公开(公告)日：2024-11-28

申请号：US18437029

申请日：2024-02-08

Applicant: Samsung Display Co., LTD.

Inventor： HYUK KIM ,  BOYONG CHUNG ,  DOO-YOUNG LEE ,  TAK-YOUNG LEE ,  SANG-UK LIM

IPC: G09G3/32 ,  G06F3/041 ,  G06F3/044

Abstract: A gate driving circuit includes a stage which outputs a scan signal based on a scan clock signal, a voltage of a first node, and a voltage of a second node, and outputs a sensing signal based on a sensing clock signal, a voltage of the first node, and a voltage of the second node. The stage includes a second sensing portion including transistors electrically connected in series and a first pull-up control portion including transistors electrically connected in series, the transistors including control electrodes electrically connected to each other. A first intermediate node between the transistors of the second sensing portion is separated from a second intermediate node between the transistors of the first pull-up control portion.

公开(公告)号：US20240161701A1

公开(公告)日：2024-05-16

申请号：US18212512

申请日：2023-06-21

Applicant: Samsung Display Co., Ltd.

Inventor： HYUK KIM ,  BOYONG CHUNG ,  JONGHEE KIM ,  DOO-YOUNG LEE ,  TAK-YOUNG LEE ,  SANG-UK LIM

IPC: G09G3/3266

CPC classification number: G09G3/3266 ,  G09G2300/0426 ,  G09G2310/08 ,  G09G2320/0233

Abstract: A display device includes a display panel and a gate driver. The gate driver includes an N-th stage (where N is a natural number) configured to output an N-th scan gate signal and output an N-th sensing gate signal. The N-th stage includes a compensator, a sixth transistor including a control electrode connected to a first node, and a ninth transistor including a control electrode connected to the first node. In a variable frequency mode, the compensator outputs a second signal to the first node in response to a first signal, and the sixth transistor does not output the N-th scan gate signal when the ninth transistor outputs the N-th sensing gate signal based on the sensing clock signal, the voltage of the first node, and the voltage of the second node.

公开(公告)号：US20240078962A1

公开(公告)日：2024-03-07

申请号：US18143011

申请日：2023-05-03

Applicant: Samsung Display Co., Ltd.

Inventor： HYUK KIM ,  JONGHEE KIM ,  DOO-YOUNG LEE ,  CHANG-SOO LEE ,  SANG-UK LIM ,  BOYONG CHUNG

IPC: G09G3/32

CPC classification number: G09G3/32 ,  G09G2300/0426 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2310/0267 ,  G09G2310/08 ,  H01L27/124

Abstract: Provided is a gate driving circuit comprising an N-th stage and an N+1-th stage. The N-th stage outputs an N-th scan gate signal based on an N-th scan clock signal, a voltage of a QN node, and a voltage of a QBN node and to output an N-th carry signal based on an N-th carry clock signal, the voltage of the QN node, and the voltage of the QBN node. The N+1-th stage outputs an N+1-th scan gate signal based on an N+1-th scan clock signal, a voltage of a QN+1 node, and the voltage of the QBN node and an N+1-th carry signal based on an N+1-th carry clock signal, the voltage of the QN+1 node, and the voltage of the QBN node. The N-th stage and the N+1-th stage share an inverting circuit. The inverting circuit controls the QBN node based on a third signal. N is a positive integer.