Abstract:
A vertical stack transistor includes: a first transistor and a second transistor, located in a vertical direction, wherein the first transistor includes a first gate electrode, a first insulating layer, a first electrode, a first channel, and a second electrode, which are sequentially stacked in the vertical direction, and the second transistor includes a second gate electrode, a second insulating layer, a third electrode, a second channel, and a fourth electrode, which are sequentially stacked in the vertical direction, wherein the second gate electrode and the second electrode are the same electrode.
Abstract:
A display device, includes: a display panel; and a driving unit configured to receive image data, analyze the image data, and determine shapes of a plurality of pixel units making up the image, wherein the plurality of pixel units include a first pixel unit including a plurality of first sub-pixels or a second pixel unit including a plurality of second sub-pixels and having a shape different from a shape of the first pixel unit, and wherein the first sub-pixels and the second sub-pixels include a 1-1st color sub-pixel configured to emit a first color, a 1-2nd color sub-pixel configured to emit the first color, a second color sub-pixel configured to emit a second color, the second color being different from the first color, and a third color sub-pixel configured to emit a third color, the third color being different from the first color and the second color.
Abstract:
A thin film transistor array panel according to an exemplary embodiment of the present invention includes a substrate and a gate electrode disposed on the substrate. A gate insulating layer is disposed on the substrate and covers the gate electrode. A semiconductor layer is disposed on the gate insulating layer and includes a channel region, a source region, and a drain region. The source and drain regions are separated from each other by the channel region. An etch stopper is disposed on the semiconductor layer. A passivation layer is disposed on the semiconductor layer and covers the etch stopper. A source electrode and a drain electrode are disposed on the passivation layer and are respectively connected to the source region and the drain region. The passivation layer includes a first sub-passivation layer including aluminum oxide (AlOx).