公开(公告)号：US11899588B2

公开(公告)日：2024-02-13

申请号：US17175607

申请日：2021-02-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Anshujit Sharma ,  Sushant Kondguli ,  Zhenhong Liu ,  Wilson Wai Lun Fung ,  Arun Radhakrishnan ,  Wayne Yamamoto

IPC: G06F12/00 ,  G06F12/0875 ,  G06F12/02 ,  G06T1/60 ,  G06T1/20

CPC classification number: G06F12/0875 ,  G06F12/0269 ,  G06T1/20 ,  G06T1/60 ,  G06F2212/604

Abstract: A graphics processing unit (GPU) includes a table located in a memory of the GPU and a cache hierarchy. The table contains an address of inactive data in a cache hierarchy of the GPU in which the inactive data is associated with an intermediate render target. The cache hierarchy is responsive to an eviction event by discarding the inactive data from the cache hierarchy without performing a writeback to a system memory associated with the GPU based on the address of the inactive data being contained in the table. The cache hierarchy may obtain the address of the inactive data from the table, and the inactive data may be located in a last-level cache of the cache hierarchy. In one embodiment, the address of inactive data in a cache hierarchy of the GPU includes a range of addresses for the inactive data.