公开(公告)号：US12118358B2

公开(公告)日：2024-10-15

申请号：US17583380

申请日：2022-01-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Son Hung Tran ,  Shyam Jagannathan ,  Timothy David Anderson

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0811 ,  G06F12/0875 ,  G06F12/0897 ,  G06F15/80 ,  G06F17/16

CPC classification number: G06F9/3016 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/383 ,  G06F9/3867 ,  G06F11/00 ,  G06F11/1048 ,  G06F12/0811 ,  G06F12/0875 ,  G06F12/0897 ,  G06F15/8015 ,  G06F9/3822 ,  G06F11/10 ,  G06F17/16 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/604

Abstract: Software instructions are executed on a processor within a computer system to configure a streaming engine with stream parameters to define a multidimensional array. The stream parameters define a size for each dimension of the multidimensional array and a specified width for a selected dimension of the array. Data is fetched from a memory coupled to the streaming engine responsive to the stream parameters. A stream of vectors is formed for the multidimensional array responsive to the stream parameters from the data fetched from memory. When the selected dimension in the stream of vectors exceeds the specified width, the streaming engine inserts null elements into each portion of a respective vector for the selected dimension that exceeds the specified width in the stream of vectors. Stream vectors that are completely null are formed by the streaming engine without accessing the system memory for respective data.

公开(公告)号：US20240078186A1

公开(公告)日：2024-03-07

申请号：US18446535

申请日：2023-08-09

Applicant: Arm Limited

Inventor： Olof Henrik Uhrenholt

IPC: G06F12/0891

CPC classification number: G06F12/0891 ,  G06F2212/604

Abstract: A method of operating a cache system is disclosed. When it is desired to evict a cache entry from the cache, a cache entry to evict from the cache is selected using an age of any compression block that the cache is caching data for, and the selected cache entry is evicted from the cache.

公开(公告)号：US20230350803A1

公开(公告)日：2023-11-02

申请号：US18346203

申请日：2023-07-01

Applicant: SK hynix Inc.

Inventor： Yong JIN ,  Jung Ki NOH ,  Seung Won JEON ,  Young Kyun SHIN ,  Keun Hyung KIM

IPC: G06F12/0806 ,  G06F12/0891 ,  G06F11/00

CPC classification number: G06F12/0806 ,  G06F12/0891 ,  G06F11/008 ,  G06F2212/604 ,  G06F2212/1032

Abstract: The present technology includes a storage device including a memory device including a first storage region and a second storage region and a memory controller configured to, in response to a write request in the first storage region from an external host, acquire data stored the first region based on a fail prediction information provided from the memory device and to perform a write operation corresponding to the write request, wherein the first storage region and the second storage region are allocated according to logical addresses of data to be stored in by requests of the external host.

公开(公告)号：US20230325324A1

公开(公告)日：2023-10-12

申请号：US17715459

申请日：2022-04-07

Applicant: Dell Products L.P.

Inventor： Ashok Tamilarasan ,  Philippe Armangau ,  Vamsi K. Vankamamidi

IPC: G06F12/1045 ,  G06F13/28

CPC classification number: G06F12/1054 ,  G06F13/28 ,  G06F2212/604

Abstract: A data storage system can include a deduplicated data cache used to store unique deduplicated data portions. Data portions can be promoted to the deduplicated data cache in connection with servicing I/O operations. Servicing the I/O operation that reads data from, or writes data to, a logical address can include determining whether a data portion stored at the logical address meets criteria for promoting the data portion to a deduplicated data cache. The criteria can include a condition that the data portion is a duplicate of content stored at multiple logical addresses, and can include a condition that the data portion has a reference count that is at least a minimum threshold where the reference count denotes a number of logical addresses at which the data portion is stored. Responsive to determining the data portion meets the criteria, the data portion can be stored in the deduplicated data cache.

公开(公告)号：US11734426B2

公开(公告)日：2023-08-22

申请号：US17064552

申请日：2020-10-06

Applicant: Ventana Micro Systems Inc.

Inventor： John G. Favor ,  Srivatsan Srinivasan

IPC: G06F21/56 ,  G06F12/0891

CPC classification number: G06F21/566 ,  G06F12/0891 ,  G06F2212/604 ,  G06F2221/034

Abstract: A microprocessor for mitigating side channel attacks includes a memory subsystem having at least a data cache memory and configured to receive a load operation that specifies a load address. The processor performs speculative execution of instructions and executes instructions out of program order. The memory subsystem, in response to detecting that the load address misses in the data cache memory: detects a condition in which the load address specifies a location for which a valid address translation does not currently exist or permission to read from the location is not allowed, and prevents cache line data implicated by the missing load address from being filled into the data cache memory in response to detection of the condition.

公开(公告)号：US11726916B1

公开(公告)日：2023-08-15

申请号：US17730473

申请日：2022-04-27

Applicant: EMC IP Holding Company, LLC

Inventor： Geng Han ,  Vladimir Shveidel ,  Uri Shabi

IPC: G06F12/08 ,  G06F12/0842 ,  G06F12/02

CPC classification number: G06F12/0842 ,  G06F12/0238 ,  G06F2212/604

Abstract: A method, computer program product, and computing system for defining a normal IO write mode for writing data to a storage system including: writing the data to a cache memory system of a first storage node, writing the data to a journal of the first storage node, sending a notification concerning the data to a second storage node, writing one or more metadata entries concerning the data to a journal of the second storage node, sending an acknowledgment signal to the host device, and writing the data to the storage array. A request may be received to enter a testing IO write mode. In response to receiving the request, the data may be written to the cache memory system. The writing of the data to the journal may be bypassed. The acknowledgment signal may be sent to the host device. The data may be written to the storage array.

公开(公告)号：US20230222067A1

公开(公告)日：2023-07-13

申请号：US17969400

申请日：2022-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soo-Young JI

IPC: G06F12/0891

CPC classification number: G06F12/0891 ,  G06F2212/604

Abstract: The present disclosure provides methods, apparatuses, and servers for cache-coherence. In some embodiments, an apparatus includes a plurality of compute express link (CXL) devices, and a switch. Each CXL device of the plurality of CXL devices includes a memory in which a portion of the memory is allocated as a cache buffer, to which different cache eviction policies are allocated. The different cache eviction policies are modified according to a cache hit ratio of the cache buffer. The switch is configured to connect the plurality of CXL devices to each other.

公开(公告)号：US11650928B2

公开(公告)日：2023-05-16

申请号：US17715734

申请日：2022-04-07

Applicant: Intel Corporation

Inventor： Altug Koker ,  Balaji Vembu ,  Joydeep Ray ,  Abhishek R. Appu

IPC: G06F12/0895 ,  G06F12/126 ,  G06F12/02 ,  G06T1/60

CPC classification number: G06F12/0895 ,  G06F12/023 ,  G06F12/126 ,  G06T1/60 ,  G06F2212/1044 ,  G06F2212/1048 ,  G06F2212/455 ,  G06F2212/604 ,  G06F2212/608

Abstract: A mechanism is described for facilitating optimization of cache associated with graphics processors at computing devices. A method of embodiments, as described herein, includes introducing coloring bits to contents of a cache associated with a processor including a graphics processor, wherein the coloring bits to represent a signal identifying one or more caches available for use, while avoiding explicit invalidations and flushes.

公开(公告)号：US20190220412A1

公开(公告)日：2019-07-18

申请号：US16362672

申请日：2019-03-24

Applicant: Purdue Research Foundation

Inventor： Ashish Ranjan ,  Swagath Venkataramani ,  Zoha Pajouhi ,  Rangharajan Venkatesan ,  Kaushik Roy ,  Anand Raghunathan

IPC: G06F12/0846 ,  G06F12/0891

CPC classification number: G06F12/0848 ,  G06F12/0238 ,  G06F12/0846 ,  G06F12/0864 ,  G06F12/0891 ,  G06F2212/1028 ,  G06F2212/604 ,  G06F2212/621 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675

Abstract: An approximate cache system is disclosed. The system includes a quality aware cache controller (QACC), a cache, a quality table configured to receive addresses and a quality specification from the processor associated with each address and further configured to provide the quality specification for each address to the QACC, wherein the QACC controls approximation is based on one or more of i) approximation through partial read operations; ii) approximation through lower read currents; iii) approximation through skipped write operations; iv) approximation through partial write operations; v) approximations through lower write duration; vi) approximation through lower write currents; and vii) approximations through skipped refreshes.

公开(公告)号：US20180314648A1

公开(公告)日：2018-11-01

申请号：US15582392

申请日：2017-04-28

Applicant: AppDynamics LLC

Inventor： Walter Ted Hulick

IPC: G06F12/14 ,  G06F9/44 ,  G06F12/0868 ,  G06F9/455 ,  G06F12/128

CPC classification number: G06F12/145 ,  G06F9/4418 ,  G06F9/4552 ,  G06F12/0868 ,  G06F12/128 ,  G06F2212/1052 ,  G06F2212/604 ,  G06F2212/621

Abstract: In one aspect, a system for controlling domain name service (DNS) caching is disclosed, the system includes a processor; a memory; and one or more modules stored in the memory and executable by a processor to perform various operations. The various operations include maintain a hard cache on a local disk that includes a file of DNS entries that persists and available for access by an application after a reboot of a Java Virtual Machine (JVM) system running the application; populate a runtime positive soft cache with the entries from the hard cache, wherein the positive soft cache represents DNS entries assumed to be successful for resolving DNS client calls from the application that persists until the reboot of the JVM system running the application; and load entries into the runtime positive soft cache populated from the hard cache in response to an application making DNS client calls.