公开(公告)号：US20230420027A1

公开(公告)日：2023-12-28

申请号：US18197084

申请日：2023-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： EUN AE LEE ,  SUNGHYE CHO ,  KIJUN LEE ,  KYOMIN SOHN ,  MYUNGKYU LEE

IPC: G11C11/406

CPC classification number: G11C11/40622 ,  G11C11/40615

Abstract: A memory device may include counters respectively corresponding to rows and each configured to count a number of accesses to a corresponding row, a refresh control circuit, a queue, and first flags respectively corresponding to the rows. The refresh control circuit may change a second flag set in a refresh period every refresh period, and determine whether to put an incoming row address into the queue based on a count value of a counter corresponding to a target row indicated by the incoming row address among the counters, a first flag value of a first flag corresponding to the target row among the first flags, and a second flag value of the second flag set in a current refresh period.