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1.发明申请公开(公告)号：US20200294558A1
公开(公告)日：2020-09-17
申请号：US16813851
申请日：2020-03-10
发明人： HAK-SOO YU , NAMSUNG KIM , KYOMIN SOHN , SEONGIL O , SUKHAN LEE
IPC分类号： G11C7/10 , G11C11/409 , G11C11/408 , G11C5/02
摘要： A memory device includes a memory cell array, signal lines, a mode selector circuit, a command converter circuit, and an internal processor. The memory cell array includes first and second memory regions. The mode selector circuit is configured to generate a processing mode selection signal for controlling the memory device to enter an internal processing mode based on the address received together with the command. The command converter circuit is configured to convert the received command into an internal processing operation command in response to activation of the internal processing mode selection signal. The internal processor is configured to perform an internal processing operation on the first memory region in response to the internal processing operation command, in the internal processing mode.
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公开(公告)号：US20200294575A1
公开(公告)日：2020-09-17
申请号：US16810344
申请日：2020-03-05
发明人： SEONGIL O , SHINHAENG KANG , NAMSUNG KIM , KYOMIN SOHN , SUKHAN LEE
IPC分类号： G11C11/4096 , G06F13/16 , G06N3/04 , G06N3/063
摘要： A memory device includes a memory bank including at least one bank group, a processor in memory (PIM) circuit including a first processing element arranged to correspond to the bank group, which processes operations by using at least one of data provided by a host and data read from the bank group, a processing element input and output (PEIO) gating circuit configured to control electric connection between a bank local IO arranged to correspond to each bank of the bank group and a bank group IO arranged to correspond to the bank group, and a control logic configured to perform a control operation so that a memory operation for the memory bank is performed or operations are processed by the PIM circuit. When the operations are processed by the first processing element, the PEIO gating circuit blocks the electric connection between the bank local IO and the bank group IO.
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公开(公告)号：US20240248850A1
公开(公告)日：2024-07-25
申请号：US18416558
申请日：2024-01-18
发明人： DAEHYUN KIM , SEONGMUK KANG , JIHO KIM , KYOMIN SOHN , YEONGGEOL SONG , KIJUN LEE , MYUNGKYU LEE , SUKHAN LEE
IPC分类号： G06F12/0891 , G06F12/126
CPC分类号： G06F12/0891 , G06F12/126
摘要： A memory system includes a system controller and a memory device. The system controller includes a memory controller configured to transmit a received address to a decoding module, and output, to the host device, decoded data. The decoding module includes a cache device and a decoder. The decoding module is configured to receive the data corresponding to the address from the memory device. The decoding module is configured transmit the data stored in the cache device to the memory controller in response to determining that the data corresponding to the address is stored in the cache device. The decoding module is configured to decode the data corresponding to the address to generate decoded data and store the decoded result in the cache device in response to determining that the data corresponding to the address is not stored in the cache device.
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公开(公告)号：US20230420027A1
公开(公告)日：2023-12-28
申请号：US18197084
申请日：2023-05-14
发明人： EUN AE LEE , SUNGHYE CHO , KIJUN LEE , KYOMIN SOHN , MYUNGKYU LEE
IPC分类号： G11C11/406
CPC分类号： G11C11/40622 , G11C11/40615
摘要： A memory device may include counters respectively corresponding to rows and each configured to count a number of accesses to a corresponding row, a refresh control circuit, a queue, and first flags respectively corresponding to the rows. The refresh control circuit may change a second flag set in a refresh period every refresh period, and determine whether to put an incoming row address into the queue based on a count value of a counter corresponding to a target row indicated by the incoming row address among the counters, a first flag value of a first flag corresponding to the target row among the first flags, and a second flag value of the second flag set in a current refresh period.
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公开(公告)号：US20240232012A1
公开(公告)日：2024-07-11
申请号：US18399864
申请日：2023-12-29
发明人： Seongmuk KANG , KYUNG-HO LEE , MYUNGKYU LEE , KI-HEUNG KIM , KYOMIN SOHN , KIJUN LEE , SUNGHYE CHO , HYONGRYOL HWANG
CPC分类号： G06F11/1068 , G11C7/06 , G11C7/1078 , G11C7/12 , G11C29/42
摘要： A memory device includes an ECC circuit that performs error correction code (ECC) encoding on input data to generate write data, and a memory cell array including a plurality of memory cells that stores the write data. The ECC circuit includes a data splitter that splits the input data into first sub-data and second sub-data, a first ECC encoder that performs ECC encoding on the first sub-data to generate first sub-parity data, a second ECC encoder that performs ECC encoding on the second sub-data to generate second sub-parity data, and a data scrambler that performs a data scrambling operation with respect to the first sub-data, the second sub-data, the first sub-parity data, and the second sub-parity data based on a structure of the memory cell array to generate the write data.
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6.发明申请公开(公告)号：US20220238148A1
公开(公告)日：2022-07-28
申请号：US17722494
申请日：2022-04-18
发明人： YOUNGCHEON KWON , SANGHYUK KWON , KYOMIN SOHN , JAEYOUN YOUN , HAESUK LEE
IPC分类号： G11C11/406 , G11C11/408
摘要： A memory device according to some aspects of the inventive concepts includes a memory cell array including a plurality of banks, at least one Processing Element (PE) connected to at least one bank selected from the plurality of banks, and a control logic configured to control an active operation in which wordlines included in each of the plurality of banks is activated, and configured to control a refresh operation in which at least one bank is refreshed, based on a PE enable signal configured to selectively enable the at least one PE.
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公开(公告)号：US20220036929A1
公开(公告)日：2022-02-03
申请号：US17504918
申请日：2021-10-19
发明人： HAK-SOO YU , NAMSUNG KIM , KYOMIN SOHN , SEONGIL O , SUKHAN LEE
IPC分类号： G11C7/10 , G11C5/02 , G11C11/408 , G11C11/409
摘要： A memory device includes a memory cell array, signal lines, a mode selector circuit, a command converter circuit, and an internal processor. The memory cell array includes first and second memory regions. The mode selector circuit is configured to generate a processing mode selection signal for controlling the memory device to enter an internal processing mode based on the address received together with the command. The command converter circuit is configured to convert the received command into an internal processing operation command in response to activation of the internal processing mode selection signal. The internal processor is configured to perform an internal processing operation on the first memory region in response to the internal processing operation command, in the internal processing mode.
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公开(公告)号：US20210193615A1
公开(公告)日：2021-06-24
申请号：US16926189
申请日：2020-07-10
发明人： YOUNGCHEON KWON , KYOMIN SOHN , YAEYOUN YOUN
IPC分类号： H01L25/065 , H01L23/538 , H01L21/66
摘要： High bandwidth memories and systems including the same may include a buffer die, a plurality of memory dies stacked on the buffer die, a plurality of dummy bump groups in edge regions of the buffer die and the plurality of memory dies, and a plurality of signal line groups. Each of the plurality of dummy bump groups includes dummy bumps spaced apart from each other between each pair of adjacent dies and configured to connect the two adjacent dies to each other. Each of the signal line groups includes a plurality of signal lines configured to transmit a corresponding signal among an input signal and a plurality of bump crack detection signals applied to an input dummy bump of each of the plurality of dummy bump groups via sequential transmission through the plurality of dummy bumps to an output dummy bump during a bump crack test operation.
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