公开(公告)号：US20240256277A1

公开(公告)日：2024-08-01

申请号：US18456874

申请日：2023-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyeongmin LEE ,  Bongjun KIM ,  Seungwon LEE ,  Hanwoong JUNG

IPC: G06F9/30

CPC classification number: G06F9/3004 ,  G06F9/30036

Abstract: A system configured to perform an operation includes: a hardware device comprising a plurality of computing modules and a plurality of memory modules arranged in a lattice form, each of the computing modules comprising a coarse-grained reconfigurable array and each of the memory modules comprising a static random-access memory and a plurality of functional units connected to the static random-access memory; and a compiler configured to divide a target operation and assign the divided target operation to the computing modules and the memory modules such that the computing modules and the memory modules of the hardware device perform the target operation.

公开(公告)号：US20240411531A1

公开(公告)日：2024-12-12

申请号：US18657062

申请日：2024-05-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bongjun KIM ,  Gyeongmin LEE ,  Hanwoong JUNG

IPC: G06F8/41 ,  G06F11/30

Abstract: An operating method of an electronic device includes: generating, based on a hardware representation of a target device, a mapping by mapping hardware components represented in the hardware representation of the target device to one or more hardware-component traits and to one or more drivers; and generating, based on the hardware representation, topology information representing a connection relationship and dependency between the hardware components of the target device represented in the hardware representation, wherein the hardware representation includes representations of the hardware components tagged with the one or more hardware-component traits and representations of the one or more drivers and a hierarchical structure between the hardware components.

公开(公告)号：US20240411532A1

公开(公告)日：2024-12-12

申请号：US18668580

申请日：2024-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyeongmin LEE ,  Bongjun KIM ,  Hanwoong JUNG

IPC: G06F8/41

Abstract: An electronic device includes a deep learning compiler configured to receive a hardware representation corresponding to a target system comprising a hierarchical structure, extract a plurality of hierarchies from the target system based on the received hardware representation, and perform iterative compilation on the plurality of extracted hierarchies.