NEAR-MEMORY OPERATOR AND METHOD WITH ACCELERATOR PERFORMANCE IMPROVEMENT

    公开(公告)号:US20240256277A1

    公开(公告)日:2024-08-01

    申请号:US18456874

    申请日:2023-08-28

    CPC classification number: G06F9/3004 G06F9/30036

    Abstract: A system configured to perform an operation includes: a hardware device comprising a plurality of computing modules and a plurality of memory modules arranged in a lattice form, each of the computing modules comprising a coarse-grained reconfigurable array and each of the memory modules comprising a static random-access memory and a plurality of functional units connected to the static random-access memory; and a compiler configured to divide a target operation and assign the divided target operation to the computing modules and the memory modules such that the computing modules and the memory modules of the hardware device perform the target operation.

    COMPILATION METHOD AND APPARATUS WITH NEURAL NETWORK

    公开(公告)号:US20230418579A1

    公开(公告)日:2023-12-28

    申请号:US18464044

    申请日:2023-09-08

    Inventor: Hanwoong JUNG

    CPC classification number: G06F8/443 G06N3/10 G06F8/451

    Abstract: A compile method for a neural network, the compile method includes receiving data related to the neural network, generating a grouped layer by grouping layers comprised in the neural network based on the data, generating a set of passes executable in parallel based on a dependency between a plurality of passes to process the neural network, generating a set of threads performing a plurality of optimization functions based on whether optimization operations performed by the optimization functions is performed independently for the layers, respectively, or sequentially based on a dependency between the layers, and performing compilation in parallel based on the grouped layer, the set of passes, and the set of threads.

    ELECTRONIC DEVICE AND METHOD WITH HARDWARE-OPTIMIZED COMPILATION

    公开(公告)号:US20240411531A1

    公开(公告)日:2024-12-12

    申请号:US18657062

    申请日:2024-05-07

    Abstract: An operating method of an electronic device includes: generating, based on a hardware representation of a target device, a mapping by mapping hardware components represented in the hardware representation of the target device to one or more hardware-component traits and to one or more drivers; and generating, based on the hardware representation, topology information representing a connection relationship and dependency between the hardware components of the target device represented in the hardware representation, wherein the hardware representation includes representations of the hardware components tagged with the one or more hardware-component traits and representations of the one or more drivers and a hierarchical structure between the hardware components.

    APPARATUS AND METHOD WITH MULTIPLE NEURAL PROCESSING UNITS FOR NEURAL NETWORK OPERATION

    公开(公告)号:US20240211744A1

    公开(公告)日:2024-06-27

    申请号:US18360160

    申请日:2023-07-27

    CPC classification number: G06N3/065 G06F15/80

    Abstract: An apparatus includes: memories storing data to perform a neural network operation; processors to generate a neural network operation result by performing a neural network operation by reading the data; and crossbars processing data transmission between the processors and the memories, wherein the crossbars include: a first crossbar of a first group processing data transmission between a first group of the processors and a first group of the memories, a second crossbar of a second group processing data transmission between a second group of the processors and a second group of the memories, wherein the first group of processors does not include any processors that are in the second group of processors and wherein the first group of memories does not include any memories that are in the second group of memories, and a third crossbar connecting the first crossbar to the second crossbar.

    COMPILATION METHOD AND APPARATUS WITH NEURAL NETWORK

    公开(公告)号:US20230091392A1

    公开(公告)日:2023-03-23

    申请号:US17691679

    申请日:2022-03-10

    Inventor: Hanwoong JUNG

    Abstract: A compile method for a neural network, the compile method includes receiving data related to the neural network, generating a grouped layer by grouping layers comprised in the neural network based on the data, generating a set of passes executable in parallel based on a dependency between a plurality of passes to process the neural network, generating a set of threads performing a plurality of optimization functions based on whether optimization operations performed by the optimization functions is performed independently for the layers, respectively, or sequentially based on a dependency between the layers, and performing compilation in parallel based on the grouped layer, the set of passes, and the set of threads.

    NEURAL NETWORK OPERATION METHOD AND APPARATUS

    公开(公告)号:US20230086316A1

    公开(公告)日:2023-03-23

    申请号:US17688288

    申请日:2022-03-07

    Abstract: A neural network operation method and apparatus are disclosed, where the network operation method including receiving data for a neural network operation, determining whether a size of the data is less than or equal to a threshold, generating stacked data by stacking a portion of the data based on the determining, and performing the neural network operation in parallel based on the stacked data.

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