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公开(公告)号：US20240256277A1
公开(公告)日：2024-08-01
申请号：US18456874
申请日：2023-08-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Gyeongmin LEE , Bongjun KIM , Seungwon LEE , Hanwoong JUNG
IPC: G06F9/30
CPC classification number: G06F9/3004 , G06F9/30036
Abstract: A system configured to perform an operation includes: a hardware device comprising a plurality of computing modules and a plurality of memory modules arranged in a lattice form, each of the computing modules comprising a coarse-grained reconfigurable array and each of the memory modules comprising a static random-access memory and a plurality of functional units connected to the static random-access memory; and a compiler configured to divide a target operation and assign the divided target operation to the computing modules and the memory modules such that the computing modules and the memory modules of the hardware device perform the target operation.
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公开(公告)号：US20220179714A1
公开(公告)日：2022-06-09
申请号：US17467890
申请日：2021-09-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hanwoong JUNG , Joonho SONG , Seungwon LEE
Abstract: A method and apparatus for scheduling a neural network operation. The method includes receiving data on a layer of a neural network, generating partitions to be assigned to cores by dividing the data, generating tiles by dividing the partitions, and scheduling an operation order of the tiles based on whether the data are shared between the cores.
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公开(公告)号：US20230418579A1
公开(公告)日：2023-12-28
申请号：US18464044
申请日：2023-09-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hanwoong JUNG
Abstract: A compile method for a neural network, the compile method includes receiving data related to the neural network, generating a grouped layer by grouping layers comprised in the neural network based on the data, generating a set of passes executable in parallel based on a dependency between a plurality of passes to process the neural network, generating a set of threads performing a plurality of optimization functions based on whether optimization operations performed by the optimization functions is performed independently for the layers, respectively, or sequentially based on a dependency between the layers, and performing compilation in parallel based on the grouped layer, the set of passes, and the set of threads.
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公开(公告)号：US20220284263A1
公开(公告)日：2022-09-08
申请号：US17378867
申请日：2021-07-19
Inventor： Hanwoong JUNG , Soonhoi HA , Donghyun KANG , Duseok KANG
IPC: G06N3/04
Abstract: A neural network operation apparatus and method is provided. The neural network operation apparatus includes a memory configured to store data for a neural network operation, and a processor configured to validate the data based on a determination that the neural network operation should be performed on the data, obtain a real memory address to perform the neural network operation based on a result of the validating and a virtual tensor address of the data, and perform the neural network operation based on the real memory address.
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公开(公告)号：US20240411531A1
公开(公告)日：2024-12-12
申请号：US18657062
申请日：2024-05-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Bongjun KIM , Gyeongmin LEE , Hanwoong JUNG
Abstract: An operating method of an electronic device includes: generating, based on a hardware representation of a target device, a mapping by mapping hardware components represented in the hardware representation of the target device to one or more hardware-component traits and to one or more drivers; and generating, based on the hardware representation, topology information representing a connection relationship and dependency between the hardware components of the target device represented in the hardware representation, wherein the hardware representation includes representations of the hardware components tagged with the one or more hardware-component traits and representations of the one or more drivers and a hierarchical structure between the hardware components.
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Patent Agency Ranking
6.发明公开公开(公告)号：US20240211744A1
公开(公告)日：2024-06-27
申请号：US18360160
申请日：2023-07-27
Inventor： Hanwoong JUNG , Soonhoi HA , Keonjoo LEE , Changjae YI
Abstract: An apparatus includes: memories storing data to perform a neural network operation; processors to generate a neural network operation result by performing a neural network operation by reading the data; and crossbars processing data transmission between the processors and the memories, wherein the crossbars include: a first crossbar of a first group processing data transmission between a first group of the processors and a first group of the memories, a second crossbar of a second group processing data transmission between a second group of the processors and a second group of the memories, wherein the first group of processors does not include any processors that are in the second group of processors and wherein the first group of memories does not include any memories that are in the second group of memories, and a third crossbar connecting the first crossbar to the second crossbar.
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公开(公告)号：US20230091392A1
公开(公告)日：2023-03-23
申请号：US17691679
申请日：2022-03-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hanwoong JUNG
Abstract: A compile method for a neural network, the compile method includes receiving data related to the neural network, generating a grouped layer by grouping layers comprised in the neural network based on the data, generating a set of passes executable in parallel based on a dependency between a plurality of passes to process the neural network, generating a set of threads performing a plurality of optimization functions based on whether optimization operations performed by the optimization functions is performed independently for the layers, respectively, or sequentially based on a dependency between the layers, and performing compilation in parallel based on the grouped layer, the set of passes, and the set of threads.
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公开(公告)号：US20230086316A1
公开(公告)日：2023-03-23
申请号：US17688288
申请日：2022-03-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Maksim OSTAPENKO , Hanwoong JUNG
Abstract: A neural network operation method and apparatus are disclosed, where the network operation method including receiving data for a neural network operation, determining whether a size of the data is less than or equal to a threshold, generating stacked data by stacking a portion of the data based on the determining, and performing the neural network operation in parallel based on the stacked data.
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公开(公告)号：US20240411532A1
公开(公告)日：2024-12-12
申请号：US18668580
申请日：2024-05-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Gyeongmin LEE , Bongjun KIM , Hanwoong JUNG
IPC: G06F8/41
Abstract: An electronic device includes a deep learning compiler configured to receive a hardware representation corresponding to a target system comprising a hierarchical structure, extract a plurality of hierarchies from the target system based on the received hardware representation, and perform iterative compilation on the plurality of extracted hierarchies.
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公开(公告)号：US20240221112A1
公开(公告)日：2024-07-04
申请号：US18524062
申请日：2023-11-30
Inventor： Hanwoong JUNG , Soonhoi HA , Donghyun KANG
IPC: G06T3/40
CPC classification number: G06T3/4046
Abstract: Neural network operation apparatus and method are provided. The neural network operation apparatus includes: one or more processors; and memory storing instructions configured to cause the one or more processors to: generate an upsampled tensor by copying pixels, of a unit of data, based on a scale factor for upsampling; and generate, based on the scale factor, a neural network operation result by performing a pooling operation on the upsampled tensor.
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