公开(公告)号：US20150199230A1

公开(公告)日：2015-07-16

申请号：US14524476

申请日：2014-10-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MI-KYOUNG PARK ,  Dong-Yang Lee ,  Sun-Young Lim ,  Bu-Il Jung ,  Ju-Yun Jung ,  Sung-Ho Cho ,  Hee-Joo Choi ,  Min-Yeab Choo ,  Hyuk Han

IPC: G06F11/10

CPC classification number: G11C29/76 ,  G11C8/06 ,  G11C2029/4402

Abstract: A memory system includes a memory controller, a memory cell array, a location information storage unit, an address mapping table, an address conversion unit, and a mapping information calculation unit. The memory controller generates a logical address signal and an address re-mapping command. The memory cell array includes a plurality of logic blocks. The location information storage unit stores location information corresponding to faulty memory cells included in the memory cell array. The address mapping table stores address mapping information. The address conversion unit converts the logical address signal to a physical address signal corresponding to the memory cell array based on the address mapping information. The mapping information calculation unit generates the address mapping information to reduce the number of logic blocks including the faulty memory cells based on the location information upon the mapping information calculation unit receiving the address re-mapping command.

Abstract translation: 存储器系统包括存储器控制器，存储单元阵列，位置信息存储单元，地址映射表，地址转换单元和映射信息计算单元。 存储器控制器产生逻辑地址信号和地址重映射命令。 存储单元阵列包括多个逻辑块。 位置信息存储单元存储与包含在存储单元阵列中的故障存储单元对应的位置信息。 地址映射表存储地址映射信息。 地址转换单元基于地址映射信息将逻辑地址信号转换为对应于存储单元阵列的物理地址信号。 映射信息计算单元根据映射信息计算单元接收地址重映射命令，根据位置信息生成地址映射信息，以减少包括故障存储单元的逻辑块的数量。

公开(公告)号：US09472305B2

公开(公告)日：2016-10-18

申请号：US14534492

申请日：2014-11-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-Yeab Choo ,  Bu-Il Jung ,  Do-Geun Kim ,  Mi-Kyoung Park ,  Dong-Yang Lee ,  Sun-Young Lim ,  Ju-Yun Jung ,  Hyuk Han

IPC: G11C29/04 ,  G11C29/00

CPC classification number: G11C29/04 ,  G11C29/78 ,  G11C29/785 ,  G11C29/88

Abstract: A method of repairing a memory device including a boot memory region, a normal memory region, and a redundant memory region, the redundant memory region including a plurality of repair memory units, includes repairing the boot memory region by performing at least one of excluding first fault memory units of the boot memory region from use as storage and replacing the first fault memory units with boot repair memory units of the repair memory units, each of the first fault memory units having at least one fault memory cell; and after the repairing the boot memory region, repairing the normal memory region by performing at least one of excluding second fault memory units from use as storage and replacing the second fault memory units with normal repair memory units of the repair memory units.

Abstract translation: 一种修复包括引导存储器区域，正常存储器区域和冗余存储器区域的存储器件的方法，所述冗余存储器区域包括多个修复存储器单元，包括通过执行以下操作中的至少一个修复引导存储器区域：排除第一 引导存储器区域的故障存储器单元用作存储，并且用修复存储器单元的引导修复存储器单元替换第一故障存储器单元，每个第一故障存储器单元具有至少一个故障存储器单元; 并且在修复引导存储器区域之后，通过执行排除第二故障存储器单元中的至少一个作为存储来修复正常存储器区域，并用修复存储器单元的正常修复存储器单元替换第二故障存储器单元。

公开(公告)号：US10083764B2

公开(公告)日：2018-09-25

申请号：US14524476

申请日：2014-10-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mi-Kyoung Park ,  Dong-Yang Lee ,  Sun-Young Lim ,  Bu-Il Jung ,  Ju-Yun Jung ,  Sung-Ho Cho ,  Hee-Joo Choi ,  Min-Yeab Choo ,  Hyuk Han

IPC: G11C29/00 ,  G11C8/06 ,  G11C29/44

CPC classification number: G11C29/76 ,  G11C8/06 ,  G11C2029/4402

Abstract: A memory system includes a memory controller, a memory cell array, a location information storage unit, an address mapping table, an address conversion unit, and a mapping information calculation unit. The memory controller generates a logical address signal and an address re-mapping command. The memory cell array includes a plurality of logic blocks. The location information storage unit stores location information corresponding to faulty memory cells included in the memory cell array. The address mapping table stores address mapping information. The address conversion unit converts the logical address signal to a physical address signal corresponding to the memory cell array based on the address mapping information. The mapping information calculation unit generates the address mapping information to reduce the number of logic blocks including the faulty memory cells based on the location information upon the mapping information calculation unit receiving the address re-mapping command.