公开(公告)号：US10236298B2

公开(公告)日：2019-03-19

申请号：US15997725

申请日：2018-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Suk Kim ,  Joon-Hee Lee ,  Kee-Jeong Rho

IPC: H01L27/11573 ,  H01L49/02 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11521 ,  H01L27/11568

Abstract: Provided is a vertical non-volatile memory device in which a capacitor constituting a peripheral circuit region is formed as a vertical type so that an area occupied by the capacitor in the entire device can be reduced as compared with a planar capacitor. Thus, a non-volatile memory device may be highly integrated and have a high capacity. The device includes a substrate having a cell region and a peripheral circuit region, a memory cell string including a plurality of vertical memory cells formed in the cell region and channel holes formed to penetrate the vertical memory cells in a first direction vertical to the substrate, an insulating layer formed in the peripheral circuit region on the substrates at substantially the same level as an upper surface of the memory cell string, and a plurality of capacitor electrodes formed on the peripheral circuit region to penetrate at least a portion of the insulating layer in the first direction, the plurality of capacitor electrodes extending parallel to the channel holes. The plurality of capacitor electrodes are spaced apart from one another in a second direction parallel to the substrate, and the insulating layer is interposed between a pair of adjacent capacitor electrodes from among the plurality of capacitor electrodes.

公开(公告)号：USD722979S1

公开(公告)日：2015-02-24

申请号：US29488336

申请日：2014-04-17

Applicant: Samsung Electronics Co., Ltd.

Designer： Hyun-Suk Kim ,  Young-Gyu Kim ,  Seok-Hyun Yoon ,  Jong-Chul Choi ,  Hyun-Ju Hong

公开(公告)号：US09207936B2

公开(公告)日：2015-12-08

申请号：US14466136

申请日：2014-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Suk Kim ,  Yong-Ha Park

IPC: G06F13/00 ,  G06T1/60 ,  G06F9/30 ,  G06F9/44

CPC classification number: G06F9/30 ,  G06F9/44 ,  G06T1/60

Abstract: A method of operating a graphic processor unit includes detecting from a program code a code area that instructs a load/store unit to load data stored in a plurality of rows of a memory to registers of a register file using a scheduler; and, using a load/store unit, loading data to the at least one register in response to instructions corresponding to the code area. A second instruction of the instructions instructs the load/store unit to write control information in a control register of the at least one register. The control information includes at least mask bits designating selected rows of the memory that store data to be loaded from the plurality of rows of the memory, a span field representing a relationship of the plurality of rows of the memory to each other and a stride field. A third instruction of the instruction instructs the load/store unit to store the data sequentially from a row of the memory corresponding to an address written in a base register of the register file to a first register of the register file, according to the control information.

Abstract translation: 一种操作图形处理器单元的方法包括：从程序代码检测指示加载/存储单元将存储在多行存储器中的数据加载到使用调度程序的寄存器文件的寄存器的代码区; 以及使用加载/存储单元，响应于与代码区域对应的指令，将数据加载到至少一个寄存器。 指令的第二指令指示加载/存储单元将控制信息写入至少一个寄存器的控制寄存器中。 所述控制信息至少包括指定存储器的选定行的屏蔽位，所述存储器的行存储从所述存储器的多行中加载的数据，所述跨度字段表示所述存储器的多行与彼此之间的关系， 。 该指令的第三指令指示加载/存储单元根据控制信息将来自与写入寄存器文件的基址寄存器的地址相对应的存储器的行的顺序存储到寄存器堆的第一寄存器 。