公开(公告)号：US08908461B2

公开(公告)日：2014-12-09

申请号：US13770538

申请日：2013-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Hun Kim ,  Inchul Jeong

IPC: G11C7/00 ,  G11C7/12 ,  G11C11/406 ,  G11C11/402

CPC classification number: G11C11/402 ,  G11C7/12 ,  G11C11/40615 ,  G11C11/40618

Abstract: A refresh circuit in a semiconductor memory device performs a multi-enable skew refresh operation during each periodic refresh operation. The refresh circuit includes a signal generation unit configured to generate a plurality of refresh signals having different timings during a refresh operation period, a first refresh circuit configured to enable refresh target lines associated with a first memory group in a memory cell array through operation periods of at least two time periods by using some of the refresh signals, and a second refresh circuit configured to enable refresh target lines associated with a second memory group differing from the first memory group through operation periods of at least two time periods by using some or all of the rest of the refresh signals. Enable timings of the first and second refresh circuits do not coincide each other.

Abstract translation: 半导体存储器件中的刷新电路在每个周期性刷新操作期间执行多使能偏斜刷新操作。 刷新电路包括：信号生成单元，被配置为在刷新操作期间生成具有不同定时的多个刷新信号;第一刷新电路，被配置为使存储单元阵列中与第一存储器组相关联的刷新目标线通过操作周期 通过使用一些刷新信号的至少两个时间段，以及第二刷新电路，被配置为通过使用一些或全部的操作来使能与第一存储器组不同的第二存储器组的刷新目标行通过至少两个时间段的操作周期 剩下的刷新信号。 启用第一和第二刷新电路的定时不一致。

公开(公告)号：US20130272082A1

公开(公告)日：2013-10-17

申请号：US13770538

申请日：2013-02-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Hun Kim ,  Inchul Jeong

IPC: G11C11/402 ,  G11C7/12

CPC classification number: G11C11/402 ,  G11C7/12 ,  G11C11/40615 ,  G11C11/40618

Abstract: A refresh circuit in a semiconductor memory device performs a multi-enable skew refresh operation during each periodic refresh operation. The refresh circuit includes a signal generation unit configured to generate a plurality of refresh signals having different timings during a refresh operation period, a first refresh circuit configured to enable refresh target lines associated with a first memory group in a memory cell array through operation periods of at least two time periods by using some of the refresh signals, and a second refresh circuit configured to enable refresh target lines associated with a second memory group differing from the first memory group through operation periods of at least two time periods by using some or all of the rest of the refresh signals. Enable timings of the first and second refresh circuits do not coincide each other.

Abstract translation: 半导体存储器件中的刷新电路在每个周期性刷新操作期间执行多使能偏斜刷新操作。 刷新电路包括：信号生成单元，被配置为在刷新操作期间生成具有不同定时的多个刷新信号;第一刷新电路，被配置为使存储单元阵列中与第一存储器组相关联的刷新目标线通过操作周期 通过使用一些刷新信号的至少两个时间段，以及第二刷新电路，被配置为通过使用一些或全部的操作来使能与第一存储器组不同的第二存储器组的刷新目标线通过至少两个时间段的操作周期 剩下的刷新信号。 启用第一和第二刷新电路的定时不一致。