公开(公告)号：US20250096175A1

公开(公告)日：2025-03-20

申请号：US18794640

申请日：2024-08-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YISEUL HAN ,  KWANG-SOO KIM ,  JAESUN KIM

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor package includes a first redistribution layer structure, a first set of semiconductor dies on the first redistribution layer structure, a plurality of connection members on the first redistribution layer structure and around the first set of semiconductor dies, a molding material on the first redistribution layer structure, the molding material covering the first set of semiconductor dies and at least partially surrounding the plurality of connection members, a second redistribution layer structure on the molding material, a second set of semiconductor dies on the second redistribution layer structure, and a dummy structure on the second redistribution layer structure and between a first semiconductor die of the second set of semiconductor dies and a second semiconductor die of the second set of semiconductor dies.

公开(公告)号：US20250096099A1

公开(公告)日：2025-03-20

申请号：US18751036

申请日：2024-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAESUN KIM ,  HEEYOUB KANG ,  EUNKYEONG PARK ,  YISEUL HAN

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor package may include a lower redistribution structure having a lower redistribution layer, a lower chip structure on the lower redistribution structure, the lower chip structure including a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a plurality of first posts on a side of the second semiconductor chip and electrically connected to the first semiconductor chip, and a first encapsulant covering the first semiconductor chip, the second semiconductor chip, and the plurality of first posts, a plurality of second posts on a side of the lower chip structure and electrically connected to the lower redistribution layer, a second encapsulant covering the lower chip structure and each of the plurality of second posts, connection vias passing through a portion of the second encapsulant, and electrically connected to the plurality of first posts, and an upper redistribution structure on the second encapsulant.

公开(公告)号：US20230170290A1

公开(公告)日：2023-06-01

申请号：US17886872

申请日：2022-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： YUN-HEE LEE ,  JAESUN KIM ,  SEOKBEOM YONG ,  WONJAE LEE

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/13 ,  H01L24/29 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/2919 ,  H01L2224/13147 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2924/0665

Abstract: Disclosed is a semiconductor package comprising a redistribution substrate and a semiconductor chip on the redistribution substrate. The redistribution substrate includes a plurality of first conductive patterns including a pair of first signal patterns that are adjacent to each other, and a plurality of second conductive patterns on surfaces of the first conductive patterns and coupled to the first conductive patterns. The second conductive patterns include a ground pattern insulated from the pair of first signal patterns. The ground pattern has an opening that penetrates the ground pattern. When viewed in plan, the pair of first signal patterns overlap the opening.