公开(公告)号：US11990435B2

公开(公告)日：2024-05-21

申请号：US17867287

申请日：2022-07-18

Applicant: Amkor Technology Singapore Holding Pte. Ltd.

Inventor： Sung Sun Park ,  Ji Young Chung ,  Christopher Berry

IPC: G06V40/13 ,  B81C3/00 ,  H01L23/00 ,  H01L23/053 ,  H01L23/31

CPC classification number: H01L24/05 ,  B81C3/00 ,  G06V40/13 ,  G06V40/1329 ,  H01L23/053 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L23/3128 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/27 ,  H01L24/29 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/16227 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/27622 ,  H01L2224/2784 ,  H01L2224/29006 ,  H01L2224/29007 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29294 ,  H01L2224/29299 ,  H01L2224/2939 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/8146 ,  H01L2224/81464 ,  H01L2224/81466 ,  H01L2224/81471 ,  H01L2224/81484 ,  H01L2224/81815 ,  H01L2224/8185 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2924/014 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/13111 ,  H01L2924/01082 ,  H01L2224/13111 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2224/13111 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2224/13111 ,  H01L2924/01029 ,  H01L2224/13111 ,  H01L2924/01047 ,  H01L2224/13111 ,  H01L2924/01079 ,  H01L2224/13111 ,  H01L2924/01083 ,  H01L2224/13111 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/13111 ,  H01L2924/01047 ,  H01L2924/01083 ,  H01L2224/13111 ,  H01L2924/0103 ,  H01L2224/13111 ,  H01L2924/0103 ,  H01L2924/01083 ,  H01L2224/11334 ,  H01L2924/00014 ,  H01L2224/1146 ,  H01L2924/00014 ,  H01L2224/1132 ,  H01L2924/00014 ,  H01L2224/11849 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05639 ,  H01L2924/00014 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05655 ,  H01L2924/00014 ,  H01L2224/0345 ,  H01L2924/00014 ,  H01L2224/03464 ,  H01L2924/00014 ,  H01L2224/03452 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2924/00014 ,  H01L2224/05139 ,  H01L2924/00014 ,  H01L2224/05144 ,  H01L2924/00014 ,  H01L2224/05155 ,  H01L2924/00014 ,  H01L2224/0347 ,  H01L2924/00014 ,  H01L2224/1147 ,  H01L2924/00014 ,  H01L2224/05666 ,  H01L2924/01074 ,  H01L2224/05671 ,  H01L2924/00014 ,  H01L2224/05666 ,  H01L2924/01028 ,  H01L2224/0361 ,  H01L2924/00014 ,  H01L2224/119 ,  H01L2224/034 ,  H01L2224/1147 ,  H01L2224/034 ,  H01L2224/114 ,  H01L2224/0361 ,  H01L2224/13294 ,  H01L2924/00014 ,  H01L2224/133 ,  H01L2924/014 ,  H01L2224/81203 ,  H01L2924/00014 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2224/2919 ,  H01L2924/0665 ,  H01L2224/2929 ,  H01L2924/0665 ,  H01L2224/2919 ,  H01L2924/07025 ,  H01L2224/2929 ,  H01L2924/07025 ,  H01L2224/2919 ,  H01L2924/069 ,  H01L2224/2929 ,  H01L2924/069 ,  H01L2224/83102 ,  H01L2924/00014 ,  H01L2224/83101 ,  H01L2924/00014 ,  H01L2224/9211 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/29294 ,  H01L2924/00014 ,  H01L2224/2939 ,  H01L2924/00014 ,  H01L2224/29299 ,  H01L2924/00014 ,  H01L2224/27622 ,  H01L2924/00014 ,  H01L2224/2732 ,  H01L2924/00014 ,  H01L2224/27312 ,  H01L2924/00014 ,  H01L2224/81447 ,  H01L2924/00014 ,  H01L2224/81424 ,  H01L2924/00014 ,  H01L2224/81455 ,  H01L2924/00014 ,  H01L2224/8146 ,  H01L2924/00014 ,  H01L2224/81439 ,  H01L2924/00014 ,  H01L2224/81464 ,  H01L2924/00014 ,  H01L2224/81484 ,  H01L2924/00014 ,  H01L2224/81444 ,  H01L2924/00014 ,  H01L2224/81466 ,  H01L2924/00014 ,  H01L2224/81471 ,  H01L2924/00014 ,  H01L2224/8185 ,  H01L2924/00012 ,  H01L2224/05166 ,  H01L2924/00014 ,  H01L2224/05684 ,  H01L2924/00014

Abstract: A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various fingerprint sensor devices, and methods of manufacturing thereof, that comprise a sensing area on a bottom side of a die without top side electrodes that senses fingerprints from the top side, and/or that comprise a sensor die directly electrically connected to conductive elements of a plate through which fingerprints are sensed.

公开(公告)号：US20240071990A1

公开(公告)日：2024-02-29

申请号：US17896030

申请日：2022-08-25

Applicant: Micron Technology, Inc.

Inventor： Kelvin Tan Aik Boo ,  Seng Kim Ye ,  Hong Wan Ng ,  Ling Pan ,  See Hiong Leow

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L24/81 ,  H01L21/4846 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13082 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13173 ,  H01L2224/13176 ,  H01L2224/13178 ,  H01L2224/1318 ,  H01L2224/13181 ,  H01L2224/13183 ,  H01L2224/13184 ,  H01L2224/16238 ,  H01L2224/81385 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81466 ,  H01L2224/81469 ,  H01L2224/81473 ,  H01L2224/81476 ,  H01L2224/81478 ,  H01L2224/8148 ,  H01L2224/81481 ,  H01L2224/81483 ,  H01L2224/81484 ,  H01L2224/81815 ,  H01L2924/3841

Abstract: A semiconductor device assembly including a semiconductor device having a plurality of pillars disposed on a backside surface of the semiconductor device; and a substrate, including: a solder mask layer disposed on a front side surface of the substrate, a plurality of extended bond pads disposed on the frontside surface of the substrate and surrounded by the solder mask layer, the plurality of extended bond pads each having a top surface higher than a top surface of the solder mask layer, and wherein the semiconductor device is directly attached to the substrate by bonding each of the plurality of pillars of the semiconductor device to the top surface of a corresponding one of the plurality of extended bond pads with a solder connection.

公开(公告)号：US20240015883A1

公开(公告)日：2024-01-11

申请号：US18340097

申请日：2023-06-23

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Shuhei Momose

IPC: H05K1/02 ,  H01L23/498 ,  H01L23/00

CPC classification number: H05K1/0296 ,  H01L23/49822 ,  H01L23/49866 ,  H01L24/81 ,  H01L2224/16227 ,  H01L24/16 ,  H01L2224/32225 ,  H01L24/32 ,  H01L2224/73204 ,  H01L24/73 ,  H01L2224/81444 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L24/05 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13113 ,  H01L24/13

Abstract: A wiring substrate includes a wiring layer, a protective insulation layer covering the wiring layer, an opening extending through the protective insulation layer and partially exposing an upper surface of the wiring layer, a first plating layer formed inside the opening on the wiring layer that is exposed in the opening, a gap extending between a side surface of the first plating layer and a wall surface of the opening, and a second plating layer entirely covering a surface of the first plating layer in the opening of the protective insulation layer. The first plating layer is formed from nickel or a nickel alloy. The second plating layer is formed from a metal having a higher resistance to oxidation than the metal forming the first plating layer. The second plating layer entirely covers a side surface of the first plating layer that is exposed in the gap.

公开(公告)号：US11749534B1

公开(公告)日：2023-09-05

申请号：US17957683

申请日：2022-09-30

Applicant: Deca Technologies USA, Inc.

Inventor： Robin Davis ,  Paul R. Hoffman ,  Clifford Sandstrom ,  Timothy L. Olson

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L21/4839 ,  H01L21/561 ,  H01L21/568 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/13147 ,  H01L2224/16245 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81457 ,  H01L2224/81466 ,  H01L2224/81469 ,  H01L2224/81481 ,  H01L2224/81484

Abstract: A method and related structure for a quad flat no-lead (QFN), dual flat no-lead (DFN) or small outline no-lead (SON) package without a leadframe. Disposing semiconductor chips face-up on a temporary carrier, disposing a first encapsulant layer around the semiconductor chip, the active layer and conductive stumps, forming a conductive layer and conductive contacts over the planar surface, disposing encapsulant over the first encapsulant layer, conductive layer and conductive contacts, forming a photoresist over the encapsulant with openings, forming conductive pads within the openings, forming a solderable metal system (SMS) or applying an organic solderability preservative (OSP) over the conductive pads, and cutting through the encapsulant around the chip to form the outline of a package.

公开(公告)号：US20180182701A1

公开(公告)日：2018-06-28

申请号：US15819310

申请日：2017-11-21

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Kei Imafuji

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/49838 ,  H01L23/3157 ,  H01L23/49866 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/13101 ,  H01L2224/1413 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81464 ,  H01L2224/83385 ,  H01L2224/92125 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A wiring board includes an insulator layer having a top surface, and a plurality of pads arranged in a pad arrangement region on the top surface of the insulator layer. The pad arrangement region includes a first region in which a first plurality of pads among the plurality of pads are arranged at a first density, and a second region in which a second plurality of pads among the plurality of pads are arranged at a second density lower than the first density. At least one dummy pad is arranged juxtaposed to at least one of the second plurality of pads in the second region of the pad arrangement region.

公开(公告)号：US10008466B2

公开(公告)日：2018-06-26

申请号：US15729127

申请日：2017-10-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroyuki Utsunomiya

IPC: H01L21/44 ,  H01L21/4763 ,  H01L23/48 ,  H01L23/52 ,  H01L23/00

CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03831 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/10145 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/13005 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81424 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81469 ,  H01L2224/81815 ,  H01L2924/206 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A flip-chip mounting technique with high reliability is provided in flip-chip mounting using a Cu pillar. In a semiconductor device to be coupled to a mounting board via a Cu pillar, the Cu pillar is caused to have a laminated structure including a pillar layer, a barrier layer, and a bump in this order from below, and the bump is formed to be smaller than the barrier layer.

公开(公告)号：US20180166426A1

公开(公告)日：2018-06-14

申请号：US15378911

申请日：2016-12-14

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： PO CHUN LIN

IPC: H01L25/10 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L25/105 ,  H01L21/563 ,  H01L23/3185 ,  H01L23/49816 ,  H01L23/562 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/0391 ,  H01L2224/05164 ,  H01L2224/05184 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05684 ,  H01L2224/1132 ,  H01L2224/11515 ,  H01L2224/131 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/2929 ,  H01L2224/29324 ,  H01L2224/29339 ,  H01L2224/29393 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/8112 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81484 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2224/92222 ,  H01L2224/92225 ,  H01L2224/92242 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2224/27 ,  H01L2924/00014 ,  H01L2924/01006

Abstract: A semiconductor structure includes a first package including a substrate and a die disposed over the substrate and electrically connected to the substrate by a first conductive bump; a second package disposed over the first package and electrically connected to the substrate by a second conductive bump; and an adhesive disposed between the die and the second package.

公开(公告)号：US09935066B2

公开(公告)日：2018-04-03

申请号：US15224977

申请日：2016-08-01

Applicant: Qorvo US, Inc.

Inventor： Thomas Scott Morris ,  Robert Hartmann

IPC: H01L27/00 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L24/05 ,  H01L23/3157 ,  H01L23/49838 ,  H01L23/5381 ,  H01L23/5382 ,  H01L24/03 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/45 ,  H01L2224/03828 ,  H01L2224/04042 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/13147 ,  H01L2224/13611 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45147 ,  H01L2224/81005 ,  H01L2224/81011 ,  H01L2224/8121 ,  H01L2224/81395 ,  H01L2224/81444 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01079 ,  H01L2924/2076

Abstract: The present disclosure relates to a semiconductor package having a substrate structure with selective surface finishes, and a process for making the same. The disclosed semiconductor package includes a substrate body, a first metal structure having a first finish area and a second finish area, a second metal structure having a third finish area, a surface finish, and a tuning wire. The first metal structure and the second metal structure are formed over the substrate body. The surface finish is provided over the first finish area of the first metal structure and at least a portion of the third finish area of the second metal structure. The surface finish is not provided over the second finish area of the first metal structure. The tuning wire is coupled between the first finish area and at least one portion of the third finish area.

公开(公告)号：US09922916B2

公开(公告)日：2018-03-20

申请号：US15174921

申请日：2016-06-06

Applicant: INTEL CORPORATION

Inventor： Sanka Ganesan ,  Zhiguo Qian ,  Robert L. Sankman ,  Krishna Srinivasan ,  Zhaohui Zhu

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/50 ,  H01L21/768 ,  H01L23/538

CPC classification number: H01L23/49811 ,  H01L21/76885 ,  H01L23/50 ,  H01L23/5386 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/1301 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13687 ,  H01L2224/14132 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16058 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81395 ,  H01L2224/81411 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2924/05042 ,  H01L2924/1434 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.

公开(公告)号：US20180012856A1

公开(公告)日：2018-01-11

申请号：US15202195

申请日：2016-07-05

Applicant: Avago Technologies General IP (Singapore) Pte. Ltd

Inventor： Deog Soon Choi ,  Ah Ron Lee ,  Hyon Mo Ku

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/09 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/03828 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/0912 ,  H01L2224/0951 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1147 ,  H01L2224/1181 ,  H01L2224/1183 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13007 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/131 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/1411 ,  H01L2224/1712 ,  H01L2224/175 ,  H01L2224/81192 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81815 ,  H05K3/34 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A semiconductor package and methods for producing the same are described. One example of the semiconductor package is described to include a substrate having a first face and an opposing second face. The package is further described to include a plurality of pads disposed on the first face of the substrate, each of the plurality of pads including a first face and an opposing second face that is in contact with the first face of the substrate. The semiconductor package is further described to include a plurality of solder-on-pad structures provided on a first of the plurality of pads.