公开(公告)号：US12210059B2

公开(公告)日：2025-01-28

申请号：US17825296

申请日：2022-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeongha Kim ,  Dongsoo Kang ,  Jaeboong Lee

IPC: G01R31/317

Abstract: A test element group (TEG) disposed adjacent to at least one memory chip on a wafer includes a ring oscillator configured to output a clock signal based on a direct current (DC) signal received through a first pad and from a test device, a first divider configured to divide the clock signal and to output a first divided signal, and a sequential circuit set configured to receive the clock signal and the first divided signal, to generate a test signal based on the clock signal and the first divided signal, and to output the test signal to the test device through a second pad. The sequential circuit set includes a sequential circuit having a configuration corresponding to at least one circuit included in the at least one die.