公开(公告)号：US10185684B2

公开(公告)日：2019-01-22

申请号：US14616845

申请日：2015-02-09

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jun Hee Yoo ,  Jaegeun Yun ,  Bub-chul Jeong ,  Dongsoo Kang

IPC分类号： G06F13/364 ,  G06F13/16 ,  G06F13/42 ,  G06F21/42

摘要： A system interconnect is provided which includes a first channel configured to transmit a plurality of control signals based on a first clock, and a second channel configured to transmit a plurality of data signals which correspond to the control signals based on a second clock. The first channel and the second channel allows a predetermined range of out-of-orderness, and the predetermined range of the out-of-orderness indicates that an order of the control signals is different from an order of the data signals which correspond to the control signals.

公开(公告)号：US09747998B2

公开(公告)日：2017-08-29

申请号：US14462843

申请日：2014-08-19

申请人： Samsung Electronics Co., Ltd.

发明人： Sua Kim ,  Dongsoo Kang ,  Chulwoo Park ,  Jun Hee Yoo ,  Hak-Soo Yu ,  Jaeyoun Youn ,  Sung Hyun Lee ,  Jinsu Jung ,  Hyojin Choi

IPC分类号： G11C17/16 ,  G11C29/02 ,  G11C29/42 ,  G11C29/44 ,  G11C17/18

CPC分类号： G11C17/16 ,  G11C17/18 ,  G11C29/027 ,  G11C29/42 ,  G11C29/44 ,  G11C29/4401 ,  G11C2029/4402

摘要： A test method of the semiconductor memory device including a memory cell array and an anti-fuse array includes detecting failed cells included in the memory cell array; determining a fail address corresponding to the detected failed cells; storing the determined fail address in a first region of the memory cell array; and reading the fail address stored in the first region to program the read fail address in the anti-fuse array. According to the test method of a semiconductor memory device and the semiconductor memory system, since the test operation can be performed without an additional memory for storing an address, the semiconductor memory device and the test circuit can be embodied by a small area.

公开(公告)号：US09606916B2

公开(公告)日：2017-03-28

申请号：US14307994

申请日：2014-06-18

申请人： Samsung Electronics Co., Ltd.

发明人： Sung Hyun Lee ,  Jun Hee Yoo ,  Dongsoo Kang ,  Il Park ,  Kiyeon Lee ,  Euicheol Lim

IPC分类号： G06F12/06

CPC分类号： G06F12/0607 ,  Y02D10/13

摘要： A memory system includes a high-bandwidth memory device, the high-bandwidth memory device having a relatively high operation bandwidth, the high-bandwidth memory device having a plurality of access channels. A low-bandwidth memory device has a relatively low operation bandwidth relative to the high-bandwidth memory device, the low-bandwidth memory device having one or more access channels. An interleaving unit performs a memory interleave operation among the plurality of access channels of the high-bandwidth memory device and an access channel of the one or more access channels of the low-bandwidth memory device.

公开(公告)号：US09348679B2

公开(公告)日：2016-05-24

申请号：US14465105

申请日：2014-08-21

申请人： Samsung Electronics Co., Ltd.

发明人： Jun Hee Yoo ,  Sung Hyun Lee ,  Dongsoo Kang ,  Sua Kim ,  Haksoo Yu ,  Jaeyoun Youn ,  Hyojin Choi

IPC分类号： G06F11/10 ,  G06F11/00 ,  G11C8/06 ,  G11C11/401 ,  G11C29/44

CPC分类号： G06F11/00 ,  G11C8/06 ,  G11C11/401 ,  G11C29/78 ,  G11C2029/4402

摘要： A bad page management system is provided to guarantee a yield of a volatile semiconductor memory device such as a DRAM. A bad page list exists in a DRAM. A page remapper in a memory controller performs a page remapping operation in parallel with a normal operation of a scheduling unit to perform a latency overhead hidden function. A chip size of the DRAM is reduced or minimized. A DRAM controller performs a latency overhead hidden function to control a DRAM.

摘要翻译： 提供了不良页面管理系统以保证诸如DRAM之类的易失性半导体存储器件的产量。 DRAM中存在不良页面列表。 存储器控制器中的页面重新映射器与调度单元的正常操作并行执行页面重映射操作，以执行延迟开销隐藏功能。 DRAM的芯片尺寸减小或最小化。 DRAM控制器执行延迟开销隐藏功能来控制DRAM。