公开(公告)号：US11895219B2

公开(公告)日：2024-02-06

申请号：US17136522

申请日：2020-12-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Soo Lim ,  Chang Kyu Seol ,  Pil Sang Yoon ,  Ji Youp Kim ,  Ju-Young Jung

IPC: H04L9/00 ,  G06N20/00 ,  G06F7/50 ,  G06F7/544 ,  H04L9/06 ,  H04L9/08 ,  H04L9/30

CPC classification number: H04L9/008 ,  G06F7/50 ,  G06F7/5443 ,  G06N20/00 ,  H04L9/0631 ,  H04L9/0891 ,  H04L9/30 ,  H04L2209/122

Abstract: An artificial intelligence calculation semiconductor device is provided. The artificial intelligence calculation semiconductor device comprising: a control unit; and a MAC (Multiply and Accumulator) calculator which executes a homomorphic encryption calculation through the control unit, wherein the MAC calculator includes an NTT (Numeric Theoretic Transform)/INTT (Inverse NTT) circuit which generates cipher texts by performing a homomorphic multiplication calculation through transformation or inverse transformation of data, a cipher text multiplier which executes a multiplication calculation between the cipher texts, a cipher text adder/subtractor which executes addition and/or subtraction calculations between the cipher texts, and a rotator which performs a cyclic shift of a slot of the cipher texts.

公开(公告)号：US11836606B2

公开(公告)日：2023-12-05

申请号：US16778168

申请日：2020-01-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin Soo Lim ,  Chang Kyu Seol ,  Jae Hun Jang ,  Hye Jeong So ,  Hong Rak Son ,  Pil Sang Yoon

IPC: G06N3/063 ,  G11C11/419 ,  G06F7/544 ,  G06N20/00

CPC classification number: G06N3/063 ,  G06F7/5443 ,  G06N20/00 ,  G11C11/419

Abstract: A storage device is provided including an interface circuit configured to receive application information from a host; a field programmable gate array (FPGA); a neural processing unit (NPU); and a central processing unit (CPU) configured to select a hardware image from among a plurality of hardware images stored in a memory using the application information, and reconfigure the FPGA using the selected hardware image. The NPU is configured to perform an operation using the reconfigured FPGA.