公开(公告)号：US11836606B2

公开(公告)日：2023-12-05

申请号：US16778168

申请日：2020-01-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin Soo Lim ,  Chang Kyu Seol ,  Jae Hun Jang ,  Hye Jeong So ,  Hong Rak Son ,  Pil Sang Yoon

IPC: G06N3/063 ,  G11C11/419 ,  G06F7/544 ,  G06N20/00

CPC classification number: G06N3/063 ,  G06F7/5443 ,  G06N20/00 ,  G11C11/419

Abstract: A storage device is provided including an interface circuit configured to receive application information from a host; a field programmable gate array (FPGA); a neural processing unit (NPU); and a central processing unit (CPU) configured to select a hardware image from among a plurality of hardware images stored in a memory using the application information, and reconfigure the FPGA using the selected hardware image. The NPU is configured to perform an operation using the reconfigured FPGA.

公开(公告)号：US09202576B2

公开(公告)日：2015-12-01

申请号：US14211077

申请日：2014-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoav Shereshevski ,  Avner Dor ,  Shmuel Dashevsky ,  Jun Jin Kong ,  Pil Sang Yoon

IPC: G11C16/04 ,  G11C16/10 ,  G11C11/56 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/3459

Abstract: A method of programming a non-volatile memory device includes; defining a set of verification voltages, setting a maximum verification voltage among verification voltages that are less than or equal to a first target programming voltage to be a target verification voltage, calculating a number of extra pulses based on the target verification voltage and the first target programming voltage, verifying whether a threshold voltage of the memory cell is equal to or greater than the target verification voltage by applying an incremental step pulse program (ISPP) pulse to the memory cell and then applying at least one verification voltage in the set of verification voltages to the memory cell, and further applying the ISPP pulse to the memory cell a number of times equal to the number of extra pulses when the threshold voltage is verified to be equal to or greater than the target verification voltage.

Abstract translation: 非易失性存储器件的编程方法包括： 定义一组验证电压，将小于或等于第一目标编程电压的验证电压之间的最大验证电压设置为目标验证电压，基于目标验证电压和第一目标计算额外脉冲数 编程电压，通过向存储单元施加增量步进脉冲程序（ISPP）脉冲，然后在验证集合中施加至少一个验证电压来验证存储器单元的阈值电压是否等于或大于目标验证电压 并且当阈值电压被验证为等于或大于目标验证电压时，进一步将ISPP脉冲施加到存储器单元等于额外脉冲数的次数。

公开(公告)号：US09691477B2

公开(公告)日：2017-06-27

申请号：US15042516

申请日：2016-02-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun Chu Oh ,  Jun Jin Kong ,  Young Bae Kim ,  Hong Rak Son ,  Pil Sang Yoon ,  Han Shin Shin

IPC: G11C13/00 ,  G11C7/10 ,  G11C11/56 ,  G11C11/16

CPC classification number: G11C13/0069 ,  G11C7/1006 ,  G11C11/1675 ,  G11C11/5607 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0035 ,  G11C13/004 ,  G11C13/0097 ,  G11C2013/0076

Abstract: A resistive memory system having a plurality of memory cells includes a memory device having a resistive memory cell array and a controller. The controller generates write data to be written to the memory cell array by encoding input data such that the input data corresponds to an erase state and a plurality of programming states that a memory cell may have. The input data is encoded such that at least one of the number of memory cells assigned a first programming state and the number of memory cells assigned a second programming state is smaller than at least one of the numbers of memory cells in the erase state and the other programming states. The first programming state has a highest resistance level among the plurality of programming states, and the second programming state has a second highest resistance level among the plurality of programming states.

公开(公告)号：US11895219B2

公开(公告)日：2024-02-06

申请号：US17136522

申请日：2020-12-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Soo Lim ,  Chang Kyu Seol ,  Pil Sang Yoon ,  Ji Youp Kim ,  Ju-Young Jung

IPC: H04L9/00 ,  G06N20/00 ,  G06F7/50 ,  G06F7/544 ,  H04L9/06 ,  H04L9/08 ,  H04L9/30

CPC classification number: H04L9/008 ,  G06F7/50 ,  G06F7/5443 ,  G06N20/00 ,  H04L9/0631 ,  H04L9/0891 ,  H04L9/30 ,  H04L2209/122

Abstract: An artificial intelligence calculation semiconductor device is provided. The artificial intelligence calculation semiconductor device comprising: a control unit; and a MAC (Multiply and Accumulator) calculator which executes a homomorphic encryption calculation through the control unit, wherein the MAC calculator includes an NTT (Numeric Theoretic Transform)/INTT (Inverse NTT) circuit which generates cipher texts by performing a homomorphic multiplication calculation through transformation or inverse transformation of data, a cipher text multiplier which executes a multiplication calculation between the cipher texts, a cipher text adder/subtractor which executes addition and/or subtraction calculations between the cipher texts, and a rotator which performs a cyclic shift of a slot of the cipher texts.

公开(公告)号：US11381382B2

公开(公告)日：2022-07-05

申请号：US17145617

申请日：2021-01-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwang Hoon Kim ,  Pil Sang Yoon

IPC: G06F11/10 ,  H04L9/00 ,  H04L9/08 ,  H04L9/30 ,  G06F12/14 ,  H04L9/06

Abstract: An operating method of a memory controller includes generating a random value using a seed, generating encrypted intermediate data by encrypting plaintext data using the random value, and storing the seed and the intermediate data in a memory device. Ciphertext data is generated using the seed and the intermediate data based on Ring Learning with Error (RLWE).