公开(公告)号：US20240194269A1

公开(公告)日：2024-06-13

申请号：US18517429

申请日：2023-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byungsoo KIM ,  Yohan LEE ,  Hyunggon KIM ,  Sang Soo PARK ,  Bongsoon LIM ,  Jin-Young CHUN

IPC: G11C16/16 ,  G11C16/04

CPC classification number: G11C16/16 ,  G11C16/0483

Abstract: A memory device includes a memory cell array having a plurality of memory blocks therein, including a target memory block. A voltage generator is provided, which is configured to generate an erase voltage and row line voltages, which are provided to the target memory block upon which an erase operation is to be performed. Control logic is provided, which is configured to control the memory cell array and the voltage generator. In addition, during operation, the erase voltage is provided to at least one of a bitline or a common source line associated with the target memory block, and a gate line of a transistor provided with the erase voltage is precharged before the erase voltage is provided to the at least one of the bitline or the common source line of the target memory block.