公开(公告)号：US20160012868A1

公开(公告)日：2016-01-14

申请号：US14658353

申请日：2015-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Ho MOON ,  Tai-Young KO ,  Hyung-Sik YOU

IPC: G11C7/06 ,  G11C7/12

CPC classification number: G11C7/065 ,  G11C7/12 ,  G11C11/4091

Abstract: A bit-line sense amplifier may include a pull-up driving circuit, a pull-down driving circuit and a latch-type sense amplifier. The pull-up driving circuit including a plurality of PMOS transistors connected between a power supply voltage line and a first driving power supply line, and may be configured to provide a first driving current on the first driving power supply line in response to an up control signal. The pull-down driving circuit may be configured to provide a second driving current on a second driving power supply line in response to a down control signal. The latch-type sense amplifier may be connected between the first driving power supply line and the second driving power supply line, and may be configured to sense and amplify a voltage difference between a bit line and a complementary bit line.

Abstract translation: 位线读出放大器可以包括上拉驱动电路，下拉驱动电路和锁存型读出放大器。 上拉驱动电路包括连接在电源电压线和第一驱动电源线之间的多个PMOS晶体管，并且可以被配置为响应于上升控制在第一驱动电源线上提供第一驱动电流 信号。 下拉驱动电路可以被配置为响应于下降控制信号在第二驱动电源线上提供第二驱动电流。 闩锁型读出放大器可以连接在第一驱动电源线和第二驱动电源线之间，并且可以被配置为感测和放大位线和互补位线之间的电压差。

公开(公告)号：US20190237390A1

公开(公告)日：2019-08-01

申请号：US16263408

申请日：2019-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soojung RHO ,  Chisung OH ,  Kyomin SOHN ,  Yong-Ki KIM ,  Jong-Ho MOON ,  SeungHan WOO ,  Jaeyoun YOUN

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538

Abstract: A semiconductor device includes first to M-th semiconductor dies stacked in a first direction. Each of the first to M-th semiconductor dies includes a substrate, first to K-th through silicon vias passing through the substrate in the first direction, and a first circuit to receive power through a power supply line electrically connected to the first through silicon via. Each of first to K-th through silicon vias of the N-th semiconductor die is electrically connected to a through silicon via of first to K-th through silicon vias of the (N+1)-th semiconductor die that is spaced apart therefrom in a plan view.