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    MEMORY DEVICE INCLUDING PROCESSING CIRCUIT, AND ELECTRONIC DEVICE INCLUDING SYSTEM ON CHIP AND MEMORY DEVICE
    1.
    发明申请
    MEMORY DEVICE INCLUDING PROCESSING CIRCUIT, AND ELECTRONIC DEVICE INCLUDING SYSTEM ON CHIP AND MEMORY DEVICE 有权

    公开(公告)号：US20210157751A1

    公开(公告)日：2021-05-27

    申请号：US16934497

    申请日：2020-07-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Hyuk KWON ,  Nam Sung KIM ,  Kyomin SOHN ,  Jaeyoun YOUN

    IPC: G06F13/16 ,  H01L25/065

    Abstract: A memory device includes a buffer die configured to receive a first broadcast command and a second broadcast command from an external device; and a plurality of core dies stacked on the buffer die. The plurality of core dies include: a first core die including a first processing circuit, a first memory cell array, a first command decoder configured to decode the first broadcast command, and a first data input/output circuit configured to output data of the first memory cell array to a common data input/output bus under control of the first command decoder; and a second core die including a second processing circuit, a second memory cell array, a second command decoder configured to decode the second broadcast command, and a second data input/output circuit configured to receive the data of the first memory cell array through the common data input/output bus under control of the second command decoder.

    MEMORY DEVICE FOR SUPPORTING NEW COMMAND INPUT SCHEME AND METHOD OF OPERATING THE SAME
    2.
    发明申请
    MEMORY DEVICE FOR SUPPORTING NEW COMMAND INPUT SCHEME AND METHOD OF OPERATING THE SAME 有权

    公开(公告)号：US20210225418A1

    公开(公告)日：2021-07-22

    申请号：US17145941

    申请日：2021-01-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Youngcheon KWON ,  Jemin RYU ,  Jaeyoun YOUN ,  Haesuk LEE ,  Jihyun CHOI

    IPC: G11C7/22 ,  G11C7/10

    Abstract: A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during 1 cycle of the clock signal, receiving a first precharge command through the row pins during a 0.5 cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during the 1.5 cycles of the clock signal, receiving a second read command or a second write command through the column pins during the 1 cycle of the clock signal, and receiving a second precharge command through the row pins during the 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal.

    SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS 有权

    公开(公告)号：US20210193245A1

    公开(公告)日：2021-06-24

    申请号：US16864787

    申请日：2020-05-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yesin RYU ,  Sanguhn CHA ,  Sunghye CHO ,  Kijun LEE ,  Myungkyu LEE ,  Youngcheon KWON ,  Jaeyoun YOUN

    IPC: G11C29/42 ,  G11C29/44 ,  G11C29/14 ,  G11C7/10

    Abstract: A semiconductor memory device includes a memory cell array and an interface circuit including an error correction code (ECC) engine. The memory cell array includes a plurality of volatile memory cells, a normal cell region and a parity cell region. The interface circuit, in a write operation, receives main data and first parity data from an external device, the first parity data being generated based on a first ECC and stores the main data in the normal cell region and the first parity data in the parity cell region. The interface circuit, in a read operation, performs an ECC decoding on the main data using a second ECC, based on the first parity data to correct a first type of error in the main data. The second ECC has a parity check matrix which is the same as a parity check matrix of the first ECC.

    MEMORY DEVICE INCLUDING PROCESSING CIRCUIT, AND ELECTRONIC DEVICE INCLUDING SYSTEM ON CHIP AND MEMORY DEVICE
    6.
    发明公开
    MEMORY DEVICE INCLUDING PROCESSING CIRCUIT, AND ELECTRONIC DEVICE INCLUDING SYSTEM ON CHIP AND MEMORY DEVICE 审中-公开

    公开(公告)号：US20240086345A1

    公开(公告)日：2024-03-14

    申请号：US18511725

    申请日：2023-11-16

    Applicant: SAMSUNG ELECTRONICS Co., LTD.

    Inventor： Sang-Hyuk KWON ,  Nam Sung KIM ,  Kyomin SOHN ,  Jaeyoun YOUN

    IPC: G06F13/16 ,  H01L25/065

    CPC classification number: G06F13/1668 ,  H01L25/0657 ,  G11C8/10

    Abstract: A memory device includes a buffer die configured to receive a first broadcast command and a second broadcast command from an external device; and a plurality of core dies stacked on the buffer die. The plurality of core dies include: a first core die including a first processing circuit, a first memory cell array, a first command decoder configured to decode the first broadcast command, and a first data input/output circuit configured to output data of the first memory cell array to a common data input/output bus under control of the first command decoder; and a second core die including a second processing circuit, a second memory cell array, a second command decoder configured to decode the second broadcast command, and a second data input/output circuit configured to receive the data of the first memory cell array through the common data input/output bus under control of the second command decoder.

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