公开(公告)号：US10740236B2

公开(公告)日：2020-08-11

申请号：US15677739

申请日：2017-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Vikas Sinha ,  Eric C. Quinnell ,  Jyotsna Kartha

IPC: G06F15/17 ,  G06F12/0831 ,  G06F15/76 ,  G06F3/06

Abstract: A method and apparatus are provided. The apparatus includes a plurality of central processing units, a plurality of core input/output units, a plurality of last level cache memory banks, an interconnect network comprising multiple instantiations of dedicated data channels, wherein each dedicated data channel is dedicated to a memory transaction type, each instantiation of dedicated data channels includes arbitration multiplexors, and each dedicated data channel operates independently of other data channels.

公开(公告)号：US20180329820A1

公开(公告)日：2018-11-15

申请号：US15677739

申请日：2017-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Vikas SINHA ,  Eric C. Quinnell ,  Jyotsna Kartha

IPC: G06F12/0831 ,  G06F15/17

Abstract: A method and apparatus are provided. The apparatus includes a plurality of central processing units, a plurality of core input/output units, a plurality of last level cache memory banks, an interconnect network comprising multiple instantiations of dedicated data channels, wherein each dedicated data channel is dedicated to a memory transaction type, each instantiation of dedicated data channels includes arbitration multiplexors, and each dedicated data channel operates independently of other data channels.