公开(公告)号：US11169810B2

公开(公告)日：2021-11-09

申请号：US16374743

申请日：2019-04-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan J. Hensley ,  Fuzhou Zou ,  Monika Tkaczyk ,  Eric C. Quinnell ,  James David Dundas ,  Madhu Saravana Sibi Govindan

IPC: G06F9/30 ,  G06F9/38

Abstract: According to one general aspect, an apparatus may include an instruction fetch unit circuit configured to retrieve instructions from a memory. The apparatus may include an instruction decode unit configured to convert instructions into one or more micro-operations that are provided to an execution unit circuit. The apparatus may also include a micro-operation cache configured to store micro-operations. The apparatus may further include a branch prediction circuit configured to: determine when a kernel of instructions is repeating, store at least a portion of the kernel within the micro-operation cache, and provide the stored portion of the kernel to the execution unit circuit without the further aid of the instruction decode unit circuit.

公开(公告)号：US10740236B2

公开(公告)日：2020-08-11

申请号：US15677739

申请日：2017-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Vikas Sinha ,  Eric C. Quinnell ,  Jyotsna Kartha

IPC: G06F15/17 ,  G06F12/0831 ,  G06F15/76 ,  G06F3/06

Abstract: A method and apparatus are provided. The apparatus includes a plurality of central processing units, a plurality of core input/output units, a plurality of last level cache memory banks, an interconnect network comprising multiple instantiations of dedicated data channels, wherein each dedicated data channel is dedicated to a memory transaction type, each instantiation of dedicated data channels includes arbitration multiplexors, and each dedicated data channel operates independently of other data channels.

公开(公告)号：US10108398B2

公开(公告)日：2018-10-23

申请号：US15809971

申请日：2017-11-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eric C. Quinnell

IPC: G06F7/485 ,  G06F7/499 ,  G06F7/50

Abstract: According to one general aspect, an apparatus may include a floating-point addition unit that includes a far path circuit, a close path circuit, and a final result selector circuit. The far path circuit may be configured to compute a far path result based upon either the addition or the subtraction of the two floating-point numbers regardless of whether the operands or the result include normal or denormal numbers. The close path circuit may be configured to compute a close path result based upon the subtraction of the two floating-point operands regardless of whether the operands or the result include normal or denormal numbers. The final result selector circuit may be configured to select between the far path result and the close path result based, at least in part, upon an amount of difference in the exponent portions of the two floating-point operands.

公开(公告)号：US10360158B2

公开(公告)日：2019-07-23

申请号：US15616917

申请日：2017-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eric C. Quinnell ,  Kevin C. Heuer ,  Tarun Nakra ,  Akhil Arunkumar

IPC: G06F12/123 ,  G06F12/0815 ,  G06F12/0891 ,  G06F12/0862

Abstract: Embodiments of the present system and method provide cache replacement in a victim exclusive cache using a snoop filter where replacement information is not lost during a re-reference back to the CPU. Replacement information is stored in a snoop filter, meaning that historical access data may be fully preserved and allows for more flexibility in the LLC re-insertion points, without additional bits stored in a L2 cache. The present system and method further include snoop filter replacement technique. The present system and method passes replacement information between a snoop filter and a victim exclusive cache (e.g., LLC) when transactions move cachelines to and from a master CPU. This maintains and advances existing replacement information for a cacheline that is removed from the victim exclusive cache on a read, as well as intelligently replaces and ages cachelines in the snoop filter.

公开(公告)号：US20180329820A1

公开(公告)日：2018-11-15

申请号：US15677739

申请日：2017-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Vikas SINHA ,  Eric C. Quinnell ,  Jyotsna Kartha

IPC: G06F12/0831 ,  G06F15/17

Abstract: A method and apparatus are provided. The apparatus includes a plurality of central processing units, a plurality of core input/output units, a plurality of last level cache memory banks, an interconnect network comprising multiple instantiations of dedicated data channels, wherein each dedicated data channel is dedicated to a memory transaction type, each instantiation of dedicated data channels includes arbitration multiplexors, and each dedicated data channel operates independently of other data channels.

公开(公告)号：US09904545B2

公开(公告)日：2018-02-27

申请号：US14856538

申请日：2015-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eric C. Quinnell

IPC: G06F9/30

CPC classification number: G06F9/30014 ,  G06F9/30036

Abstract: According to one general aspect, an apparatus may include a monolithic shifter configured to receive a plurality of bytes of data, and, for each byte of data, a number of bits to shift the respective byte of data, wherein the number of bits for each byte of data need not be the same as for any other byte of data. The monolithic shifter may be configured to shift each byte of data by the respective number of bits. The apparatus may include a mask generator configured to compute a mask for each byte of data, wherein each mask indicates which bits, if any, are to be prevented from being polluted by a neighboring shifted byte of data. The apparatus may include a masking circuit configured to combine the shifted byte of data with a respective mask to create an unpolluted shifted byte of data.

公开(公告)号：US10564963B2

公开(公告)日：2020-02-18

申请号：US15901873

申请日：2018-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eric C. Quinnell

IPC: G06F9/30

Abstract: According to one general aspect, an apparatus may include a monolithic shifter configured to receive a plurality of bytes of data, and, for each byte of data, a number of bits to shift the respective byte of data, wherein the number of bits for each byte of data need not be the same as for any other byte of data. The monolithic shifter may be configured to shift each byte of data by the respective number of bits. The apparatus may include a mask generator configured to compute a mask for each byte of data, wherein each mask indicates which bits, if any, are to be prevented from being polluted by a neighboring shifted byte of data. The apparatus may include a masking circuit configured to combine the shifted byte of data with a respective mask to create an unpolluted shifted byte of data.