公开(公告)号：US20190130987A1

公开(公告)日：2019-05-02

申请号：US16007528

申请日：2018-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-yong CHOI ,  Kyung-ryun KIM ,  Woong-dai KANG ,  Hyun-chul YOON

IPC: G11C29/12 ,  G11C11/408 ,  G11C11/4094

CPC classification number: G11C29/12 ,  G11C11/4085 ,  G11C11/4094 ,  G11C29/04 ,  G11C29/24 ,  G11C2029/1202 ,  G11C2029/1204

Abstract: A memory device including a memory cell array connected to a first bit line, first word lines, and second word lines, the memory cell array including a first memory cell and a second memory cell, the first memory cell being connected between the first word lines and the first bit line, and the second memory cell being connected between the second word line and the first bit line; a first word line driver configured to drive the first word lines; a second word line driver configured to drive the second word lines; and a test manager configured to drive second word lines to change a capacitance of the first bit line, and after the capacitance of the first bit line is changed, drive first word lines to test the first word lines.