公开(公告)号：US20170213731A1

公开(公告)日：2017-07-27

申请号：US15342151

申请日：2016-11-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-chul YOON ,  Kyoung-seon KIM ,  Hai-sub NA ,  Jin PARK

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/02 ,  H01L21/027

CPC classification number: H01L21/0337 ,  H01L21/02118 ,  H01L21/02282 ,  H01L21/02299 ,  H01L21/02318 ,  H01L21/02345 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/3105 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/11582 ,  H01L28/00

Abstract: A method of manufacturing a semiconductor device includes forming a feature layer on a substrate, forming a plurality of reference patterns, arranged at a first pitch, on the feature layer, forming an organic liner on a side wall of each of the plurality of reference patterns, forming a plurality of buried patterns on the organic liner, removing the organic liner exposed between the plurality of buried patterns and the plurality of reference patterns, and etching the feature layer by using the plurality of buried patterns and the plurality of reference patterns as etch masks to form a feature pattern. Each of the plurality of buried patterns covers a space between side walls of two adjacent reference patterns among the plurality of reference patterns.

公开(公告)号：US20190130987A1

公开(公告)日：2019-05-02

申请号：US16007528

申请日：2018-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-yong CHOI ,  Kyung-ryun KIM ,  Woong-dai KANG ,  Hyun-chul YOON

IPC: G11C29/12 ,  G11C11/408 ,  G11C11/4094

CPC classification number: G11C29/12 ,  G11C11/4085 ,  G11C11/4094 ,  G11C29/04 ,  G11C29/24 ,  G11C2029/1202 ,  G11C2029/1204

Abstract: A memory device including a memory cell array connected to a first bit line, first word lines, and second word lines, the memory cell array including a first memory cell and a second memory cell, the first memory cell being connected between the first word lines and the first bit line, and the second memory cell being connected between the second word line and the first bit line; a first word line driver configured to drive the first word lines; a second word line driver configured to drive the second word lines; and a test manager configured to drive second word lines to change a capacitance of the first bit line, and after the capacitance of the first bit line is changed, drive first word lines to test the first word lines.