公开(公告)号：US10386410B2

公开(公告)日：2019-08-20

申请号：US15464334

申请日：2017-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Lawrence H. Rubin ,  David C. Tannenbaum

IPC: G01R31/28 ,  G01R31/317 ,  G06F11/00

Abstract: According to one general aspect, an apparatus may include a plurality of performance and debug monitoring circuits (PDMCs). Each performance and debug monitoring circuit (PDMC) may include an input stage, a combinatorial stage, and a counter. The input stage may be configured to receive a plurality of input signals, wherein the input signals include: signals from other performance and debug monitoring circuits, signals from combinatorial logic circuits, and configuration values. The combinatorial stage may be configured to perform one or more logical operations on a selected sub-set of the input signals. The counter may be configured to increment based, at least in part, upon a result of the combinatorial stage.

公开(公告)号：US10310012B2

公开(公告)日：2019-06-04

申请号：US15473593

申请日：2017-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Lawrence H. Rubin ,  David C. Tannenbaum

IPC: G01R31/28 ,  G01R31/317 ,  G06F11/00

Abstract: According to one general aspect, an apparatus may include an interconnect bus, an interconnect-to-debug bus interface, and a debug bus. The interconnect bus may be configured to connect and manage combinatorial logical blocks during normal operation of a processor and operate synchronous to a core clock. The interconnect-to-debug bus interface may be configured to translate communications between the interconnect bus and the debug bus. The debug bus may include a plurality of debug wrapper circuits arranged in a daisy chain for unidirectional communication, and configured to operate synchronous to the core clock. Each of the plurality of debug wrapper circuits may be configured to: identify if the respective debug wrapper circuit is activated by the debug bus, receive a non-invasive input from a respective combinatorial logic block, and place the non-invasive input from the respective combinatorial logic block on the debug bus.