公开(公告)号：US20170048087A1

公开(公告)日：2017-02-16

申请号：US15099987

申请日：2016-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEON-KYOO LEE ,  Jeong-Don IHM ,  Anil KAVALA ,  Byung-Hoon JEONG

IPC: H04L25/03

CPC classification number: H04L25/03019 ,  H04L25/03114 ,  H04L27/01 ,  H04L2025/03535

Abstract: An equalizer circuit may include an equalizer controller and a plurality of equalizers. The equalizer controller may prove separate sets of enable signals, delay control signals and voltage control signals to the separate equalizers based on a control signal. The equalizers provide equalizer signals to separate connection nodes between separate pairs of logic circuits. An equalizer may be selectively activated based on a received enable signal. An equalizer may include a delay control circuit and a voltage control circuit. The delay control circuit may delay a received transfer signal to generate a delayed transfer signal based on a received delay control signal. The voltage control circuit may generate an equalizer signal based on the delayed transfer signal and a received voltage control signal. The equalizer circuit may reduce inter-symbol interference in the integrated circuit based on providing the equalizer signals to the connection nodes between the logic circuits.

Abstract translation: 均衡器电路可以包括均衡器控制器和多个均衡器。 均衡器控制器可以基于控制信号向单独的均衡器证明单独的使能信号组，延迟控制信号和电压控制信号。 均衡器提供均衡器信号以在单独的逻辑电路对之间分离连接节点。 可以基于接收到的使能信号来选择性地激活均衡器。 均衡器可以包括延迟控制电路和电压控制电路。 延迟控制电路可以延迟接收到的传送信号，以基于接收的延迟控制信号产生延迟的传送信号。 电压控制电路可以基于延迟的传送信号和接收的电压控制信号产生均衡器信号。 均衡器电路可以通过将均衡器信号提供给逻辑电路之间的连接节点来减小集成电路中的符号间干扰。