公开(公告)号：US20170288717A1

公开(公告)日：2017-10-05

申请号：US15397012

申请日：2017-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seon-Kyoo LEE ,  Byung-Hoon JEONG ,  Jeong-Don IHM ,  Young-Don CHOI

IPC: H04B1/24 ,  H04L25/03 ,  H04L12/863

CPC classification number: H04B1/24 ,  H04L25/0292 ,  H04L25/0298 ,  H04L25/03847 ,  H04L25/03878 ,  H04L47/6235 ,  H04L49/90

Abstract: A reception interface circuit includes a termination circuit, a buffer and an interface controller. The termination circuit is configured to change a termination mode in response to a termination control signal. The buffer is configured to change a reception characteristic in response to a buffer control signal. The interface controller is configured to generate the termination control signal and the buffer control signal such that the reception characteristic of the buffer is changed in association with the change in the termination mode. The reception interface circuit may support various communication standards by changing the reception characteristic of the buffer in association with the termination mode. Using the reception interface circuit, communication efficiency of transceiver systems such as a memory system and/or compatibility between a transmitter device and a receiver device may be improved.

公开(公告)号：US20210320039A1

公开(公告)日：2021-10-14

申请号：US17356152

申请日：2021-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Jae LEE ,  Sang-Lok KIM ,  Byung-Hoon JEONG ,  Tae-Sung LEE ,  Jeong-Don IHM ,  Jae-Yong JEONG ,  Young-Don CHOI

IPC: H01L21/66 ,  H01L23/528 ,  G01R31/3187

Abstract: A semiconductor device includes a semiconductor die, a defect detection structure and an input-output circuit. The semiconductor die includes a central region and a peripheral region surrounding the central region. The peripheral region includes a left-bottom corner region, a left-upper corner region, a right-upper corner region and a right-bottom corner region. The defect detection structure is formed in the peripheral region. The defect detection structure includes a first conduction loop in the left-bottom corner region, a second conduction loop in the right-bottom corner region, a third conduction loop in the left-bottom corner region and the left-upper corner region and a fourth conduction loop in the right-bottom corner region and the right-upper corner region. The input-output circuit is electrically connected to end nodes of the first conduction loop, the second conduction loop, the third conduction loop and the fourth conduction loop.

公开(公告)号：US20180315461A1

公开(公告)日：2018-11-01

申请号：US16026286

申请日：2018-07-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seon-Kyoo LEE ,  Jeong-Don IHM ,  Byung-Hoon JEONG ,  Dae-Woon KANG

IPC: G11C7/14 ,  G11C7/10 ,  G11C29/02 ,  G11C29/44

CPC classification number: G11C7/14 ,  G11C7/1057 ,  G11C7/1084 ,  G11C29/021 ,  G11C29/028 ,  G11C29/4401

Abstract: A semiconductor device, includes at least a first memory chip, which includes at least a first buffer connected to receive an input signal and a reference voltage; at least a first reference voltage generator configured to output a reference voltage based on a first control code; and at least a first self-training circuit for determining an operational reference voltage to use during a normal mode of operation of the semiconductor device. An output from the first buffer is input to the first self-training circuit, the first control code is output from the first self-training circuit into the first reference voltage generator, and the first buffer, the first self-training circuit, and the first reference voltage generator form a loop.

公开(公告)号：US20170048087A1

公开(公告)日：2017-02-16

申请号：US15099987

申请日：2016-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEON-KYOO LEE ,  Jeong-Don IHM ,  Anil KAVALA ,  Byung-Hoon JEONG

IPC: H04L25/03

CPC classification number: H04L25/03019 ,  H04L25/03114 ,  H04L27/01 ,  H04L2025/03535

Abstract: An equalizer circuit may include an equalizer controller and a plurality of equalizers. The equalizer controller may prove separate sets of enable signals, delay control signals and voltage control signals to the separate equalizers based on a control signal. The equalizers provide equalizer signals to separate connection nodes between separate pairs of logic circuits. An equalizer may be selectively activated based on a received enable signal. An equalizer may include a delay control circuit and a voltage control circuit. The delay control circuit may delay a received transfer signal to generate a delayed transfer signal based on a received delay control signal. The voltage control circuit may generate an equalizer signal based on the delayed transfer signal and a received voltage control signal. The equalizer circuit may reduce inter-symbol interference in the integrated circuit based on providing the equalizer signals to the connection nodes between the logic circuits.

Abstract translation: 均衡器电路可以包括均衡器控制器和多个均衡器。 均衡器控制器可以基于控制信号向单独的均衡器证明单独的使能信号组，延迟控制信号和电压控制信号。 均衡器提供均衡器信号以在单独的逻辑电路对之间分离连接节点。 可以基于接收到的使能信号来选择性地激活均衡器。 均衡器可以包括延迟控制电路和电压控制电路。 延迟控制电路可以延迟接收到的传送信号，以基于接收的延迟控制信号产生延迟的传送信号。 电压控制电路可以基于延迟的传送信号和接收的电压控制信号产生均衡器信号。 均衡器电路可以通过将均衡器信号提供给逻辑电路之间的连接节点来减小集成电路中的符号间干扰。

公开(公告)号：US20150213873A1

公开(公告)日：2015-07-30

申请号：US14558072

申请日：2014-12-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hye-Yoon JOO ,  Seung-Jun BAE ,  Young-Soo SOHN ,  Ho-Sung SONG ,  Jeong-Don IHM

IPC: G11C11/4076 ,  G11C11/408 ,  G11C11/409 ,  H03L7/089 ,  H03L7/087

CPC classification number: H03L7/087 ,  G11C7/222 ,  H03L7/07 ,  H03L7/083 ,  H03L7/0995

Abstract: An injection-locked phase-locked loop (ILPLL) circuit includes a delay-locked loop (DLL) and an ILPLL. The DLL is configured to generate a DLL clock by performing a delay-locked operation on a reference clock. The ILPLL includes a voltage-controlled oscillator (VCO), and is configured to generate an output clock by performing an injection synchronous phase-locked operation on the reference clock. The DLL clock is injected into the VCO as an injection clock of the VCO.

Abstract translation: 注射锁相环（ILPLL）电路包括延迟锁定环（DLL）和ILPLL。 DLL被配置为通过对参考时钟执行延迟锁定操作来生成DLL时钟。 ILPLL包括压控振荡器（VCO），并且被配置为通过对参考时钟执行注入同步锁相操作来产生输出时钟。 将DLL时钟作为VCO的注入时钟注入到VCO中。

公开(公告)号：US20190198067A1

公开(公告)日：2019-06-27

申请号：US16113500

申请日：2018-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seon-Kyoo LEE ,  Dae-Hoon NA ,  Jeong-Don IHM ,  Byung-Hoon JEONG ,  Young-Don CHOI

IPC: G11C7/10 ,  G11C7/22 ,  G11C7/06 ,  H01L25/065

CPC classification number: G11C7/1051 ,  G11C7/06 ,  G11C7/065 ,  G11C7/08 ,  G11C7/1048 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/14 ,  G11C7/222 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06586 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: An apparatus includes data transmitter having first through N-th data drivers configured to provide first through N-th data signals, respectively, and a strobe driver configured to provide a strobe signal, and a data receiver having a strobe buffer configured to generate a control signal based on the strobe signal, and first through N-th sense amplifiers configured to sense N-bit data based on the control signal, a reference signal and the first through N-th data signals. The bus includes a strobe TSV configured to connect the strobe driver with the strobe buffer, and first through N-th data TSVs configured to connect the first through N-th data drivers with the first through N-th sense amplifiers, respectively. A reference signal supplier controls the reference signal such that a discharge speed of the reference signal is slower than a discharge speed of each of the first through N-th data signals during data transmission.

公开(公告)号：US20180004281A1

公开(公告)日：2018-01-04

申请号：US15426526

申请日：2017-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-Woon KANG ,  Siddharth KATARE ,  Jeong-Don IHM

IPC: G06F1/32 ,  G11C5/14 ,  G11C7/10

CPC classification number: G06F1/3296 ,  G06F1/3275 ,  G06F1/3287 ,  G11C5/145 ,  G11C5/147 ,  G11C7/1084 ,  G11C29/021 ,  G11C29/022 ,  G11C29/028 ,  Y02D10/14

Abstract: A reception interface circuit includes a reception buffer, a voltage generation circuit and a reception limiting circuit. The reception buffer receives an input signal through an input-output node to generate a buffer signal. The voltage generation circuit generates at least one control voltage based on a reflection characteristic at the input-output node. The reception limiting circuit is connected to the input-output node and limits at least one of a maximum voltage level and a minimum voltage level of the input signal based on the at least one control voltage. Power consumption may be reduced by limiting at least one of the maximum voltage level and the minimum voltage level of the input signal based on the reception characteristic at the input-output node using the reception limiting circuit, and an increased eye margin may be provided in comparison with a conventional termination circuit having the same power consumption.

公开(公告)号：US20170287535A1

公开(公告)日：2017-10-05

申请号：US15333468

申请日：2016-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seon-Kyoo LEE ,  Jeong-Don IHM ,  Byung-Hoon JEONG ,  Dae-Woon KANG

IPC: G11C7/14 ,  G11C7/10

CPC classification number: G11C7/14 ,  G11C7/1057 ,  G11C7/1084 ,  G11C29/021 ,  G11C29/028 ,  G11C29/4401

Abstract: A semiconductor device, includes at least a first memory chip, which includes at least a first buffer connected to receive an input signal and a reference voltage; at least a first reference voltage generator configured to output a reference voltage based on a first control code; and at least a first self-training circuit for determining an operational reference voltage to use during a normal mode of operation of the semiconductor device. An output from the first buffer is input to the first self-training circuit, the first control code is output from the first self-training circuit into the first reference voltage generator, and the first buffer, the first self-training circuit, and the first reference voltage generator form a loop.