公开(公告)号：US20190035756A1

公开(公告)日：2019-01-31

申请号：US15867075

申请日：2018-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUN JI MIN ,  Seokhyun LEE ,  Jongyoun KIM ,  Kyoung Lim SUK ,  SeokWon LEE

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10

Abstract: A method of fabricating a semiconductor package including, forming a preliminary first insulating layer including a first opening, curing the preliminary first insulating layer to form a first insulating layer, forming a preliminary second insulating layer on the first insulating layer at least partially filling the first opening. The method includes forming a second opening in the preliminary second insulating layer at least partially overlapping the first opening. A sidewall of the first opening is at least partially exposed during forming the second opening. The preliminary second insulating layer is cured to form a second insulating layer. A barrier metal layer is formed along the sidewall of the first opening and along a sidewall of the second opening. A redistribution conductive pattern is formed on the barrier metal layer. A planarization process is performed to at least partially expose the second insulating layer.

公开(公告)号：US20200098716A1

公开(公告)日：2020-03-26

申请号：US16698117

申请日：2019-11-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youn Ji MIN ,  Seokhyun LEE ,  Jongyoun KIM ,  Kyoung Lim SUK ,  SeokWon LEE

IPC: H01L23/00 ,  H01L21/683 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10

Abstract: A semiconductor package includes: a redistribution substrate; a semiconductor chip on the redistribution substrate; and an external terminal on a bottom surface of the redistribution substrate, wherein the redistribution substrate comprises: a first insulating layer including a first opening; a second insulating layer on the first insulating layer and including a second opening, wherein the second opening is positioned in the first opening in a plan view; a first barrier metal layer disposed along a sidewall of the first opening and along a sidewall of the second opening; a first redistribution conductive pattern on the first barrier metal layer; a third insulating layer on a bottom surface of the first insulating layer; and a pad penetrating the third insulating layer and electrically connecting to the first redistribution conductive pattern, wherein the external terminal is provided on the pad, wherein the second insulating layer at least partially covers a chip pad of the semiconductor chip, and the second opening at least partially exposes the chip pad, wherein, inside the second insulating layer, the first barrier metal layer is in contact with the chip pad through the second opening, and wherein the first redistribution conductive pattern has a surface roughness including protrusions extending in a range of from about 0.01 μm to about 0.5 μm, and the first insulating layer has a surface roughness smaller than the surface roughness of the first redistribution conductive pattern.