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公开(公告)号：US20240347435A1
公开(公告)日：2024-10-17
申请号：US18748765
申请日：2024-06-20
发明人： Hyeonjeong Hwang , Kyounglim SUK , Seokhyun LEE
IPC分类号： H01L23/498 , H01L23/00 , H01L25/065 , H01L25/10
CPC分类号： H01L23/49822 , H01L23/49816 , H01L23/49833 , H01L23/49838 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/48 , H01L25/0657 , H01L25/105 , H01L2224/16235 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204
摘要： A semiconductor package includes a semiconductor chip, a lower redistribution layer disposed under the semiconductor chip, the lower redistribution layer including a plurality of lower insulating layers, a plurality of lower redistribution patterns, and a plurality of lower conductive vias, a lower passivation layer disposed under the lower redistribution layer and provided with a recess at a bottom surface of the lower passivation layer, an under bump metallization (UBM) pad disposed in the first recess, a UBM protective layer disposed in the first recess and connected to the lower conductive vias while covering a top surface and opposite side surfaces of the UBM pad, and an outer connecting terminal connected to a bottom surface of the UBM pad. The bottom surface of the UBM pad is positioned at a first depth from the bottom surface of the lower passivation layer.
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公开(公告)号：US20240021608A1
公开(公告)日：2024-01-18
申请号：US18478056
申请日：2023-09-29
发明人： Kyoung Lim SUK , Seokhyun LEE , Jaegwon JANG
IPC分类号： H01L27/08 , H01L23/522 , H01L23/538 , H01L23/00
CPC分类号： H01L27/0805 , H01L23/5222 , H01L23/5386 , H01L24/14 , H01L28/60
摘要： Disclosed is a semiconductor package including: a redistribution substrate; at least one passive device in the redistribution substrate, the passive device including a first terminal and a second terminal; and a semiconductor chip on a top surface of the redistribution substrate, the semiconductor chip vertically overlapping at least a portion of the passive device, wherein the redistribution substrate includes: a dielectric layer in contact with a first lateral surface, a second lateral surface opposite to the first lateral surface, and a bottom surface of the passive device; a lower conductive pattern on the first terminal; a lower seed pattern provided between the first terminal and the conductive pattern, and directly connected to the first terminal; a first upper conductive pattern on the second terminal and a first upper seed pattern provided between the second terminal and the first upper conductive pattern, and directly connected to the second terminal
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公开(公告)号：US20220157810A1
公开(公告)日：2022-05-19
申请号：US17359110
申请日：2021-06-25
发明人： Kyoung Lim SUK , Seokhyun LEE , Jaegwon JANG
IPC分类号： H01L27/08 , H01L23/00 , H01L23/538 , H01L23/522 , H01L49/02
摘要： Disclosed is a semiconductor package including: a redistribution substrate; at least one passive device in the redistribution substrate, the passive device including a first terminal and a second terminal; and a semiconductor chip on a top surface of the redistribution substrate, the semiconductor chip vertically overlapping at least a portion of the passive device, wherein the redistribution substrate includes: a dielectric layer in contact with a first lateral surface, a second lateral surface opposite to the first lateral surface, and a bottom surface of the passive device; a lower conductive pattern on the first terminal; a lower seed pattern provided between the first terminal and the conductive pattern, and directly connected to the first terminal; a first upper conductive pattern on the second terminal and a first upper seed pattern provided between the second terminal and the first upper conductive pattern, and directly connected to the second terminal
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公开(公告)号：US20190378795A1
公开(公告)日：2019-12-12
申请号：US16136622
申请日：2018-09-20
发明人： Seokhyun LEE , Kyung Suk OH
IPC分类号： H01L23/522 , H01L23/498 , H01L23/538 , H01L23/367 , H01L21/768 , H01L23/00
摘要： A semiconductor package including a package substrate, a semiconductor chip on a first surface of the package substrate, a connection substrate on the package substrate and spaced apart from and surrounding the semiconductor chip, the connection substrate including a plurality of conductive connection structures penetrating therethrough, a plurality of first connecting elements between the semiconductor chip and the package substrate and electrically connecting the semiconductor chip to the package substrate, a plurality of second connecting elements between the connection substrate and the package substrate and electrically connecting the connection substrate to package substrate, a mold layer encapsulating the semiconductor chip and the connection substrate, and an upper redistribution pattern on the mold layer and the semiconductor chip and electrically connected to a corresponding one of the plurality of conductive connection structures may be provided.
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公开(公告)号：US20180076123A1
公开(公告)日：2018-03-15
申请号：US15603859
申请日：2017-05-24
发明人： Jongyoun KIM , Seokhyun LEE
CPC分类号： H01L22/32 , H01L21/486 , H01L23/3128 , H01L23/49811 , H01L23/5384 , H01L23/5389 , H01L25/105 , H01L2224/18 , H01L2225/1023 , H01L2225/1058 , H01L2924/181 , H01L2924/00012
摘要： A semiconductor package including a redistribution substrate, and a semiconductor chip mounted on the redistribution substrate, the semiconductor chip having a conductive pad on one surface thereof may be provided. The redistribution substrate may include a first passivation pattern on the conductive pad, the first passivation pattern exposing a portion of the conductive pad, and a redistribution pattern covering the portion of the conductive pad exposed by the first passivation pattern and surrounding the first passivation pattern.
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公开(公告)号：US20240136341A1
公开(公告)日：2024-04-25
申请号：US18356682
申请日：2023-07-21
发明人： Seokgeun AHN , Daewoo KIM , Seokhyun LEE
CPC分类号： H01L25/105 , H01L23/3128 , H01L23/481 , H01L23/5383 , H01L24/08 , H01L25/50 , H01L2224/08225
摘要： A semiconductor package, comprising: a first redistribution wiring layer including first and second surfaces opposite to each other, wherein the first redistribution wiring layer includes a first chip mounting region and a second chip mounting region adjacent to the first chip mounting region; a connection layer on the first surface of the first redistribution wiring layer; a first semiconductor chip on the first chip mounting region on the connection layer; a second semiconductor chip spaced apart from the first semiconductor chip on the second chip mounting region on the connection layer, wherein the second semiconductor chip includes through electrodes; a molding member on the first and second semiconductor chips on the connection layer; and a second redistribution wiring layer on the molding member, wherein the second redistribution wiring layer is electrically connected to the first redistribution wiring layer through the through electrodes.
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公开(公告)号：US20210020600A1
公开(公告)日：2021-01-21
申请号：US16748138
申请日：2020-01-21
发明人： Yeonho JANG , Gwangjae JEON , Dongkyu KIM , Jungho PARK , Seokhyun LEE
摘要： Provided is a method of manufacturing a semiconductor package including providing a carrier substrate, providing sacrificial layer on the carrier substrate, the sacrificial layer including a first sacrificial layer and a second sacrificial layer, providing a redistribution wiring layer on the sacrificial layer, providing a plurality of semiconductor chips on the redistribution wiring layer, providing a mold layer provided on the sacrificial layer, the redistribution wiring layer, and the plurality of semiconductor chips, detaching the first sacrificial layer from the second sacrificial layer, and dicing the second sacrificial layer, the redistribution wiring layer, and the mold layer, wherein a diameters of the first sacrificial layer and the second sacrificial layer are respectively less than a diameter of the carrier substrate, and a diameter of the mold layer is greater than the diameter of the redistribution wiring layer and less than the diameter of the first sacrificial layer.
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公开(公告)号：US20170294360A1
公开(公告)日：2017-10-12
申请号：US15630934
申请日：2017-06-22
发明人： Sundae KIM , Yun-Rae CHO , Namgyu BAEK , Seokhyun LEE
IPC分类号： H01L21/66 , H01L21/768
CPC分类号： H01L22/32 , H01L21/76877 , H01L21/822 , H01L22/14 , H01L22/34 , H01L23/485 , H01L23/5226 , H01L23/528 , H01L27/10897
摘要： Provided is a semiconductor device including an interconnection structure provided on a cell region of a substrate to include a first line and a second line sequentially stacked on the substrate, and a defect detection structure provided on a peripheral region of the substrate to include first and second defect detection lines provided at the same levels as those of the first and second lines, respectively.
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公开(公告)号：US20160233171A1
公开(公告)日：2016-08-11
申请号：US14985379
申请日：2015-12-30
发明人： Sundae KIM , Yun-Rae CHO , Namgyu BAEK , Seokhyun LEE
IPC分类号： H01L23/544
CPC分类号： H01L22/32 , H01L21/76877 , H01L21/822 , H01L22/14 , H01L22/34 , H01L23/485 , H01L23/5226 , H01L23/528 , H01L27/10897
摘要： Provided is a semiconductor device including an interconnection structure provided on a cell region of a substrate to include a first line and a second line sequentially stacked on the substrate, and a defect detection structure provided on a peripheral region of the substrate to include first and second defect detection lines provided at the same levels as those of the first and second lines, respectively.
摘要翻译： 本发明提供一种半导体器件，其包括设置在基板的单元区域上的互连结构，包括依次层叠在基板上的第一线和第二线，以及设置在基板的周边区域上的缺陷检测结构，包括第一和第二 缺陷检测线分别与第一和第二线的级别相同。
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公开(公告)号：US20230033087A1
公开(公告)日：2023-02-02
申请号：US17682465
申请日：2022-02-28
发明人： Kyoung Lim SUK , Taewon YOO , Seokhyun LEE
IPC分类号： H01L23/498 , H01L25/10 , H01L23/00 , H01L23/538 , H01L21/48
摘要： A semiconductor package is provided. The semiconductor package includes a first substrate including a first, second and third under-bump patterns; a semiconductor chip provided on the first substrate; conductive structures provided on the first substrate; and a second substrate provided on the semiconductor chip and the conductive structures. The third under-bump pattern is electrically isolated from the first and second under-bump patterns. The conductive structures include: a first conductive structure coupled to the first under-bump pattern; a second conductive structure coupled to the second under-bump pattern; and a third conductive structure coupled to the third under-bump pattern and provided adjacent to the first and second conductive structures. The third conductive structure is provided between the first conductive structure and the second conductive structure, the first under-bump pattern is wider than the third under-bump pattern, and the second under-bump pattern is wider than the third under-bump pattern.
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