公开(公告)号：US20230133763A1

公开(公告)日：2023-05-04

申请号：US17868126

申请日：2022-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunyoung Lee ,  Sohyeon Bae ,  Wonchul Lee

IPC: H01L27/108

Abstract: A semiconductor device includes a substrate having a cell array region, a peripheral circuit region, and a connection region, a device separation region including a first device separation layer defining a cell active region on the cell array region, a second device separation layer defining a peripheral active region on the peripheral circuit region, and a third device separation layer defining an active dam on the connection region, a gate structure including a gate electrode crossing the cell active region on the cell array region, extending into the third device separation layer on the connection region, and having an end surface in the third device separation layer, and a gate contact plug electrically connected to the gate electrode on the connection region, wherein the third device separation layer includes a first insulating liner, a second insulating liner on the first insulating liner, and an embedded insulating layer.

公开(公告)号：US11917812B2

公开(公告)日：2024-02-27

申请号：US17484679

申请日：2021-09-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sohyeon Bae ,  Wonchul Lee ,  Jaehyun Kim ,  Jaehyuk Jang ,  Hyebin Choi

IPC: H10B12/00 ,  H01L23/528

CPC classification number: H10B12/315 ,  H01L23/528

Abstract: A semiconductor device includes a gate structure and a contact plug. The gate structure extends in a first direction parallel to the substrate, and includes a first conductive pattern, a second conductive pattern and a gate mask sequentially stacked. The contact plug contacts an end portion in the first direction of the gate structure, and includes a first extension portion extending in a vertical direction and contacting sidewalls of the gate mask and the second conductive pattern, a second extension portion under and contacting the first extension portion and a sidewall of the first conductive pattern, and a protrusion portion under and contacting the second extension portion. A bottom of the protrusion portion does not contact the first conductive pattern. A first slope of a sidewall of the first extension portion is greater than a second slope of a sidewall of the second extension portion.