公开(公告)号：US10224114B2

公开(公告)日：2019-03-05

申请号：US15600715

申请日：2017-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Je-min Ryu ,  Hak-soo Yu ,  Reum Oh ,  Seong-young Seo ,  Soo-jung Rho

IPC: G11C29/12 ,  G11C5/00 ,  G11C29/26 ,  G11C29/54

Abstract: A memory device may include a memory cell array including a plurality of memory cells, and an internal operation circuit configured to perform a test operation in a test mode using a parallel bit operation of simultaneously comparing a plurality of bits and also perform an internal operation including a comparison operation with respect to external data in a normal mode other than the test mode using the parallel bit operation.