公开(公告)号：US20180358358A1

公开(公告)日：2018-12-13

申请号：US15801797

申请日：2017-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Kwan YU ,  Won Hyung KANG ,  Hyo Jin KIM ,  Sung Bu MIN

IPC: H01L27/088 ,  H01L27/02 ,  H01L29/04 ,  H01L29/06 ,  H01L29/36 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L29/165 ,  H01L21/762

CPC classification number: H01L27/0886 ,  H01L21/76224 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0207 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/36 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/7853

Abstract: The semiconductor device includes a first fin-type pattern and a second fin-type pattern which extends along a first direction; a first gate structure and a second gate structure extending in a second direction, on the first fin-type pattern and the second fin-type pattern; and a shared epitaxial pattern which connects the first fin-type pattern and the second fin-type pattern between the first gate structure and the second gate structure. An upper surface of the shared epitaxial pattern includes a first shared slope and a second shared slope which connect the first gate structure and the second gate structure, a third shared slope which is in contact with the first gate structure and connects the first shared slope and the second shared slope, and a fourth shared slope which is in contact with the second gate structure and connects the first shared slope and the second shared slope.