公开(公告)号：US09806081B2

公开(公告)日：2017-10-31

申请号：US14970465

申请日：2015-12-15

Applicant: Samsung ELectronics Co., Ltd.

Inventor： Sung Soo Yim

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L27/10852 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/90

Abstract: A semiconductor device includes a substrate with cell and peripheral regions and capacitors provided on the cell region. The cell region may include a plurality of sub-cell blocks, which are spaced apart from each other by a plurality of sub-peripheral regions, and on which the capacitors are provided. Each of the sub-peripheral regions may have a width that is two to five times a distance between centers of an adjacent pair of the capacitors.

公开(公告)号：US12211892B2

公开(公告)日：2025-01-28

申请号：US18396302

申请日：2023-12-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Jin Kim ,  Sung Soo Yim

IPC: H01L27/108 ,  H01B12/00 ,  H01L49/02 ,  H10B12/00

Abstract: A method of manufacturing a semiconductor device includes sequentially stacking a mold layer and a supporter layer on a substrate, forming a plurality of capacitor holes passing through the mold layer and supporter layer, forming a plurality of lower electrodes filling the capacitor holes, forming a supporter mask pattern having a plurality of mask holes on the supporter layer and the lower electrodes, and forming a plurality of supporter holes by patterning the supporter layer. Each of the plurality of lower electrodes has a pillar shape, and each of the mask holes is between four adjacent lower electrodes and has a circular shape.

公开(公告)号：US11245001B2

公开(公告)日：2022-02-08

申请号：US16556786

申请日：2019-08-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Jin Kim ,  Sung Soo Yim

IPC: H01L49/02 ,  H01L27/108

Abstract: A method of manufacturing a semiconductor device includes sequentially stacking a mold layer and a supporter layer on a substrate, forming a plurality of capacitor holes passing through the mold layer and supporter layer, forming a plurality of lower electrodes filling the capacitor holes, forming a supporter mask pattern having a plurality of mask holes on the supporter layer and the lower electrodes, and forming a plurality of supporter holes by patterning the supporter layer. Each of the plurality of lower electrodes has a pillar shape, and each of the mask holes is between four adjacent lower electrodes and has a circular shape.

公开(公告)号：US11881502B2

公开(公告)日：2024-01-23

申请号：US17489961

申请日：2021-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Jin Kim ,  Sung Soo Yim

IPC: H01L27/108 ,  H01L49/02 ,  H10B12/00

CPC classification number: H01L28/90 ,  H10B12/033 ,  H10B12/315

Abstract: A method of manufacturing a semiconductor device includes sequentially stacking a mold layer and a supporter layer on a substrate, forming a plurality of capacitor holes passing through the mold layer and supporter layer, forming a plurality of lower electrodes filling the capacitor holes, forming a supporter mask pattern having a plurality of mask holes on the supporter layer and the lower electrodes, and forming a plurality of supporter holes by patterning the supporter layer. Each of the plurality of lower electrodes has a pillar shape, and each of the mask holes is between four adjacent lower electrodes and has a circular shape.