Method for placing parallel multiplier

    公开(公告)号:US10002219B2

    公开(公告)日:2018-06-19

    申请号:US15068931

    申请日:2016-03-14

    CPC classification number: G06F17/505 G06F17/5072

    Abstract: A method for placing a parallel multiplier with a placement and routing tool includes receiving a datapath netlist about the parallel multiplier, extracting locations of primary input cells and primary output cells from the datapath netlist using a structure analysis module, mapping the primary input cells and the primary output cells on a specific array using the placement and routing tool, and arranging columns of the primary input cells and the primary output cells based on physical sizes of the primary input cells. The columns are arranged using the placement and routing tool. The size of the specific array is determined according to a number of the primary input cells.

    Method of fabricating semiconductor device

    公开(公告)号:US09846754B2

    公开(公告)日:2017-12-19

    申请号:US15079640

    申请日:2016-03-24

    CPC classification number: G06F17/505 G06F17/5068

    Abstract: A semiconductor device can be manufactured based on patterning groups to include a metal layer patterned according to separate patterning groups. The patterning groups are based on a layout pattern. Preparing the layout pattern includes selecting a first power pattern and a second power pattern, selecting a first pattern and a second pattern therebetween, and selecting a tie-connection pattern to connect the first power pattern to the first pattern. The manufacturing includes forming metal lines according to the patterning groups. Photomasks are manufactured according to the layout pattern, and the metal lines are formed according to the photomasks. A first photomask is manufactured based on the first power pattern and the second power pattern, the first pattern, and the tie-connection pattern, and a second photomask is manufactured based on the second pattern.

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