公开(公告)号：US20150243733A1

公开(公告)日：2015-08-27

申请号：US14605041

申请日：2015-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-gil YANG ,  Sang-su KIM ,  Tae-yong KWON

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: A semiconductor device comprises at least two nanowire patterns over a substrate, wherein the at least two nanowire patterns have increasingly narrower widths as they extend away from the substrate and have different channel impurity concentrations. A gate electrode surrounds at least a part of the at least two nanowire patterns. A gate dielectric film is disposed between the at least two nanowire patterns and the gate electrode.

Abstract translation: 半导体器件在衬底上包括至少两个纳米线图案，其中当它们远离衬底延伸并且具有不同的沟道杂质浓度时，至少两个纳米线图案具有越来越窄的宽度。 栅电极围绕至少两个纳米线图案的至少一部分。 栅电介质膜设置在至少两个纳米线图案和栅电极之间。