公开(公告)号：US20160148944A1

公开(公告)日：2016-05-26

申请号：US14919083

申请日：2015-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tea Kwang YU ,  Yong Tae KIM ,  Jae Hyun PARK ,  Kyong Sik YEOM

IPC: H01L27/115

CPC classification number: H01L27/11536 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/7881

Abstract: A method of manufacturing a semiconductor device may include forming split gate structures including a floating gate electrode layer and a control gate electrode layer in a cell region of a substrate including the cell region and a logic region adjacent to the cell region. The method may include sequentially forming a first gate insulating film and a metal gate film in the logic region and the cell region, removing the metal gate film from at least a portion of the cell region and the logic region, forming a second gate insulating film on the first gate insulating film from which the metal gate film has been removed, forming a gate electrode film on the logic region and the cell region, and forming a plurality of memory cell elements disposed in the cell region and a plurality of circuit elements disposed in the logic region.

Abstract translation: 半导体器件的制造方法可以包括在包括单元区域的基板的单元区域和与单元区域相邻的逻辑区域中形成包括浮置栅电极层和控制栅极电极层的分割栅极结构。 该方法可以包括在逻辑区域和单元区域中顺序地形成第一栅极绝缘膜和金属栅极膜，从单元区域和逻辑区域的至少一部分去除金属栅极膜，形成第二栅极绝缘膜 在去除了金属栅极膜的第一栅极绝缘膜上，在逻辑区域和单元区域上形成栅电极膜，并且形成设置在单元区域中的多个存储单元元件和设置在多个电路元件中的多个电路元件 在逻辑区域。